Abstract: A method and a system are provided for planning feedthrough ports on a floorplan for an integrated circuit. In one example, the system groups paths (e.g., nets) into mutually exclusive families of paths (e.g., nets). The system analyzes the simpler path combinations for each path family. Advantageously, the system can find consistent design solutions for paths (e.g., nets), while adding fewer ports and fewer nets, within a practical amount of time.
Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
Type:
Grant
Filed:
April 1, 2011
Date of Patent:
November 24, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Quincy Kun-Hsu Shen, Mike Mon Yen Tsai, Steven Wang
Abstract: The present disclosure relates to a computer-implemented method for iteratively solving a constraint satisfaction problem. The method may include assigning a value to each of one or more variables associated with the constraint satisfaction problem, each of the one or more variables having a first domain. The method may also include identifying an invalid solution resulting from a first value assigned to a first variable. The method may further include replacing the first value with a second value assigned to the first variable. The method may also include, upon identifying the invalid solution, generating a second domain larger than the first domain.
Type:
Grant
Filed:
November 1, 2012
Date of Patent:
November 17, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Marat Teplitsky, Efrat Gavish, Kalev Alpernas
Abstract: Embodiments of the present disclosure may include receiving, at one or more computing devices, the electronic circuit design, wherein the electronic circuit design includes at least one Unified Power Format file. Embodiments may further include generating, using the one or more computing devices, a schematic of a power supply network, based upon, at least in part, the at least one Unified Power Format file, the schematic including one or more power supply network components.
Type:
Grant
Filed:
July 10, 2013
Date of Patent:
November 17, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Philip Benedict Giangarra, Michael James Floyd, Leonardo Valencia, Debra Jean Wimpey, Yonghao Chen
Abstract: Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of interest may be projected onto a boundary of the region of interest, to determine the valid interval(s) on along the boundary. The valid intervals may then be used by a router to implement the multi-strands of interconnects. The router also considers the physical, electrical, and manufacturing requirement(s) in implementing the multi-strands of interconnects.
Type:
Grant
Filed:
December 4, 2012
Date of Patent:
November 10, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Jeffrey S. Salowe, Viral Mankad, Supriya Ananthram
Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.
Type:
Grant
Filed:
March 31, 2014
Date of Patent:
November 10, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
David Guoqing Zhang, Erik S. Panu, Levent Caglar
Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.
Type:
Grant
Filed:
September 1, 2014
Date of Patent:
November 3, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Ziyad E. Hanna, Per Anders M. Franzen, Ross M. Weber, Habeeb A. Farah, Rajeev K. Ranjan
Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for creating or manipulating electrical data sets for an electronic design across multiple abstraction levels. The method identifies simulation result(s) obtained from simulation run(s) for an electronic circuit or at least a portion thereof, identifies at least a part of one or more sets of simulation results, each of which is obtained from a simulation run for the electronic circuit or at least a portion thereof at the first abstraction level, identify relevant electrical data or information for design under test instance(s) of a master library or a master cell and creates electrical data set(s), generates a view for at least some of the electrical data set(s), and hand-off the electrical data set(s) to second abstraction level. The method may further identify preexisting electrical data set(s). The method may further compare the electrical data set(s) and preexisting electrical data set(s).
Type:
Grant
Filed:
October 26, 2011
Date of Patent:
November 3, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Prakash Krishnan, Wilfred Vance Kenzle, Akshat Shah
Abstract: Disclosed is a method, system, and computer program product for implementing efficient access to stream data. The present approach implements a stream reader that supports either reading the entire layout (e.g., loading the contents of the user-specified top cell and all its progeny) into memory, or just a portion of it (e.g., loading only the contents of the user-specified top cell and its progeny that overlapped a user-specified bounding box). Some approaches provide a mechanism to implement parallelized or multithreaded reads of the stream data.
Type:
Grant
Filed:
September 29, 2009
Date of Patent:
October 20, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Udayan Anand Gumaste, Roland Ruehl, Jeffrey Markham
Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
Abstract: Various aspects described herein create tessellated regions by identifying tessellation lines in one or more directions based at least on fixed shape(s) or route(s). New cells or shapes are added to the design by aligning at least some of the boundary segments of the new cells or shapes with existing tessellation lines. Tessellation lines are dynamically adjustable. At least some tessellated regions are associated with initial or tentative track pattern labels some of which are iteratively updated during implementation of the design. Multiple candidate track patterns may be ranked based on consistency costs to determine a tentative track pattern. Designs may be implemented with a trackless approach in trackless region(s) followed by a tracked approach based at least in part upon the initial or tentative labels that are dynamically adjusted during implementation. Capacities and demands are assessed at boundary segments of cells by using the tracked or trackless approach.
Abstract: A method for automatically performing a double patterning (DP) color-seeding check in order to discover color-seeding violations in an IC design layout. The method of some embodiments receives a layer of the IC design layout and performs an analysis on the layer of the design layout to determine several error paths. Each error path connects two color-seeding shapes that have a color-seeding violation. For each pair of shapes that has a color-seeding violation, the method of some embodiments displays a DP color-seeding violation marker on a graphical user interface (GUI) to visually assist a user to resolve the color-seeding violation.
Abstract: A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.
Type:
Grant
Filed:
March 31, 2014
Date of Patent:
October 13, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Scott Huss, Chris Moscone, James Vandersand, Jr.
Abstract: A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the reachability analysis. Coverage information is generated indicating an amount of formal verification coverage provided by the property. The coverage information is generated based on a first set of the classified cover items that correspond to the cone of influence of the property and that are reached within a particular bound during the reachability analysis.
Type:
Grant
Filed:
November 6, 2013
Date of Patent:
October 13, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Rajeev K. Ranjan, Ross M. Weber, Habeeb A. Farah, Ziyad E. Hanna
Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.
Abstract: The invention is directed to a method, computer program product and apparatus for generating modular, hierarchical code from block diagram notations. The generated code for a block preserves the hierarchical structure of the block, and is independent of where this block is embedded. Therefore, code for a block need to be generated only once, and then stored and reused multiple times, each time the block is reused in a diagram.
Abstract: A system and method are provided for boosting a selective portion of a drive signal for chip-to-chip transmission across an interconnection interface. The system includes a driver unit generating a drive signal responsive to an input data signal. The drive signal is provided on to at least one output node for transmission through the device interconnection interface, and defines a peak amplitude during a drive period. A boosting unit is coupled to the driver unit for selectively boosting a portion of the drive signal. The boosting unit actuates responsive to the input data signal to selectively apply a boost signal in self-timed manner to the drive signal, so as to thereby augment the drive signal in amplitude over a selected portion of the drive period thereof. In this manner, the boosting unit maintains the peak amplitude of the drive signal at or above a predetermined level throughout the drive period.
Abstract: Disclosed are methods, systems, and articles of manufactures for providing evolving information in generating a physical design with custom conductivity using force models and design space decomposition by first presenting a layout area in an interface. The interface then displays the evolution of the physical design in the interface to reflect temporal states of the physical design during generation of the physical design after the system receives an input for the physical design and a request for creating the physical design.
Type:
Grant
Filed:
March 15, 2013
Date of Patent:
September 22, 2015
Assignee:
Cadence Design Systems, Inc.
Inventors:
Thaddeus C. McCracken, Joseph P. Jarosz
Abstract: Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files.