Abstract: A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Abstract: The present invention introduces novel methods generating training data for machine learning models that will be used for extraction. Specifically, experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases. The training point set then used to train a machine learning built model such as a neural network or support vector machine that will extract electrical characteristics.

Abstract: The invention is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.

Abstract: Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit (“IC”) layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.

Abstract: Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit (“IC”) design layout. The method receives a set of nets. Each net in the set has a set of routable elements in the IC design-layout region. For each net, the method then specifies a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes.

Abstract: Some embodiments provide a method of routing nets in a region of an integrated-circuit layout. This method initially identifies a characteristic of the region, and then selects a wiring model from a set of wiring models, based on the identified characteristic. Each wiring models specifies a set of routing directions. The method then routes the nets based on the selected wiring model.

Abstract: To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is then determined for each allocated design point. From a subset of the allocated design points, a plurality of new design points is generated for the circuit. The cost for each new design point is then determined and each new design point having a cost that is the same or more favorable than the most favorable cost associated with the allocated design points is allocated to the design population. The design points allocated to the design population can then be displayed for selection of one of said allocated design points having desired performances of the circuit.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit (“IC”) layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net's routable elements.

Abstract: A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements or performs a set of two or more functions. Some embodiments provide a method for producing a circuit description of a design that (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the replacement sub-network in certain conditions. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Abstract: A visualization and data mining technique can be utilized to facilitate analysis of generated sets of design points for an integrated circuit to enable easy and fast understanding of important properties of generated designs. The use of the visualization and data mining technique significantly reduces the time needed for analysis of design space and decision on which design point to choose for implementing into a circuit design.

Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular net and each particular edge, identifies an edge-intersect probability that specifies the probability that a set of potential routes for the particular net will intersect the particular edge, and (2) uses the identified edge-intersect probabilities to identify routes for the nets. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. In other embodiments, the method partitions the region into several sub-regions that have a number of paths between them.

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract: Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit (“IC”) design layout. The region contains at least one net with several routable elements. The method decomposes the IC design-layout region into a tessellated graph. The tessellated graph includes a plurality of edges. The method then specifies a route that connects the net's routable elements by specifying a set of edges that the route intersects.

Abstract: One embodiment of the invention is a method of routing a group of nets in a region. The method identifies a first route for a first net. It then determines whether embedding the first route in the region will make a set of unrouted nets in the region unroutable. When embedding the first route will make the set of unrouted nets unroutable, the method then identifies a second route for the first net. If embedding a route will not make the set of unrouted nets unroutable, the method embeds the route in the region.

Abstract: Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The space has several dimensional states. The method identifies several pairs of wedge vectors. Each vector has a tail, and each wedge-vector pair includes two vectors that are connected at their tails. The method assigns locations in the first state for the tails of at least some of the identified wedge-vector pairs. The method then uses the wedge-vector pairs that have assigned tail locations to propagate the first cost function.

Abstract: A method for use by a placement and routing tool automatically selects positions for all n I/O buffers of an IC from among a set of m available legal positions for such buffers within an IC layout so as to best meet a set of criteria affected by I/O buffer placement. The method initially establishes a weighted cost function ci,j quantifying a cost, relative to that set of criteria, of assigning the ith I/O buffer to the jth legal position. The weighted cost function is then evaluated with respect to each possible combination of i and j to produce an m×n cost data matrix indicating all costs associated with all of the m×n possible I/O buffer placements. The cost data matrix is then analyzed to produce a placement plan assigning each I/O buffer to a separate legal position in a way that minimizes a total cost of the buffer placement with respect to the set of criteria. The method may also be used to assign I/O pads among a set of legal pad positions.

Abstract: Some embodiments of the invention provide a method of routing nets in an integrated-circuit layout region that has multiple interconnect layers. The method specifies several routes, where some of the routes utilize vias to traverse multiple interconnect layers. The method assesses a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit.

Abstract: A design verifier includes a bounded model checker, a proof partitioner and a fixed-point detector. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If a counterexample is found, the bounded model checker selectively increases K and verifies the property to the new larger depth using the original constraints. If no counterexample is found, the proof partitioner provides an over-approximation of the states reachable in one or more steps using a proof generated by the bounded model checker. The fixed-point detector detects whether the over-approximation is at a fixed point. If the over-approximation is at a fixed-point, the design is verified. If the over-approximation is not at a fixed point, the bounded model checker can iteratively use over-approximations as a constraint and verify the property to a depth K.

Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex extraction sub problems, machine learning is used to build models. In one embodiment, Support Vector Machines are constructed to extract the desired electrical characteristics.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse multiple interconnect layers. The method then moves at least one via to improve the routing.