Abstract: A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of the system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to be optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions.

Abstract: A termination synthesis technique that automatically derives an optimum termination scheme for interconnects in electronic circuits. The termination synthesis technique uses an adaptive partitioning approach to divide a large circuit into separate clusters that can be independently terminated. The technique can thus automatically derive the optimum termination type and location for large and complex circuits.

Abstract: A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.

Abstract: A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.

Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Abstract: A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions. The constraint graph is then expanded by replacing edges having piecewise linear cost function with subgraphs constructed from the piecewise linear cost function.

Abstract: A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, includes the steps of: determining a dominator edge and dominated gates in the circuit, the dominated gates coupled to the first primary input lead and to edges of the plurality of edges dominated by the dominator edge; providing a dominator selector circuit to the circuit; coupling the dominator selector circuit to the dominator edge and to the first primary input lead; uncoupling the dominated gates from the first primary input lead; and coupling the dominated gates to the dominator selector circuit.

Abstract: A behavioral description translation method is disclosed wherein output and input access functions are identified from behavioral descriptions of the underlying circuit and its components. Structural representations of the behavioral descriptions of the circuits components as identified by the access functions are constructed therefrom from a set of branch primitives provided. From the constructed branches, those S-type branches, i.e., voltage sources and current probes, that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches are collapsed. Those P-type branches, i.e., the current sources and voltage probes, that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches are collapsed.

Abstract: The system and method improves Electronic Design Automation practices by creating a data template representing pins, elements, and dependencies for numerous components in the same functional class. A pin having the same function is represented once on the data template even if the pin name is different. Sequences of component pins having the same function are combined and are represented by a single pin on the data template. The performance of functional logic symbol generation systems increases significantly because the data template enables the creation of functional logic symbols to be accomplished quickly, accurately, and consistently.

Abstract: A device extractor for extracting devices from a hierarchical cell design. The device extractor selects a cell from the lowest level of the hierarchy and searches the cell for the device components. The device extractor searches each cell in the lowest level and then selects a "parent" cell in the penultimate level. The parent cell, and all of the children cells of the parent cell, are searched. The selection and search process continues until all of the components of the device are identified in a cell or the children cell of the cell and a proper relationship between the components is determined. The components of the identified device are masked so that they are not identified and associated with another device during subsequent searches.

Abstract: A computer-aided engineering and design (CAE/CAD) tool for defining and verifying a system definition provides an improved technique for modeling multi-disciplinary signals. Terminals within the system definition have associated quantities (voltage, current, energy, velocity, flux, flow, acceleration, heat, weight, length, etc.) from diverse disciplines (e.g., electrical, mechanical, thermal, optical, chemical, and fluidic etc.). A strength (e.g., "indifferent", "suggest", "insist", or "overide") is also associated with each terminal. The quantities of each terminal are nominated to be the quantities of a node the terminal is connected to. When conflicting quantities are assigned to a common node in the system (i.e., a plurality of terminals with different associated quantities connect to the same node), rules based on the associated terminal strengths are applied to resolve the conflict. An initial node quantity and node strength are assigned to the common node based on the resolution of the conflict.

Abstract: A ratiometric Fourier analyzer is provided for determining the frequency components of the output waveforms of electronic circuits by eliminating errors due to aliasing without increasing the time necessary for analysis. Ratiometric Fourier analyzers in accordance with the present invention detect values of an output waveform from a circuit simulator at time intervals selected according to features of the output waveform being analyzed. A functional representation of the output waveform over each interval is generated using a polynomial fit to the detected values of the waveform, and a Fourier integral for each frequency of interest is calculated for interval using the functional representation of the waveform. The Fourier integrals are then summed over the intervals of the output waveform to yield the Fourier coefficient at a given frequency for the output waveform.

Abstract: A method is disclosed for deriving code schedule sequences for a target code generator from an input ordering of nodes and prime factors of their respective ordered invocation rates from an SDF graph representative of a system. The method involves first creating a loop set for each prime factor wherein the elements of each loop set are the actors, the invocation frequency from which are factorable by that prime factor and are ordered. The redundant created loop sets are merged so as to eliminate those sets with identical nodes. The merged loop sets are then sorted in decreasing order by the total number of node elements in each set. A determination is then made as to whether each loop set is a proper subset of its sorted ordered predecessor loop set with which it intersects and, if not, then breaking the non-disjoint sets into sublists of sets which are proper subsets of their predecessor sets and then determining whether the parent sets of the broken sublists are then disjoint from one another.

Abstract: A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.

Abstract: A method and system for verifying design constraints on printed circuit boards and multichip modules provides for user programmability and design of new constraints and applicable verification procedures for verifying the constraints. New constraints are defined, identifying various attributes dealing with the circuit elements to which the constraint is applied, and precedence of the constraint with respect to existing constraints on circuit element. A verification procedure is defined for the constraint, and the verification procedure is registered in a constraint verification library such that it can be retrieved when an circuit element is supplied to a verification engine for verification of applicable design constraints on the circuit element.

Abstract: Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

Abstract: Overconstraints in a system, such as an electrical circuit layout, are identified using port abstraction graphs. Intercell pitchmatching constraints are represented by meta-edges between cells. Classes of edges which can be represented by a support edge are created, and the value of the class edges are increased to the value of the support edge. The edge values are updated in the graphs, and the redundant edges eliminated. Overconstraints are identified as positive cycles in the graphs, and a database of the layout is annotated and graphically displayed. The graphical display responds to user inputs to manipulate the display of the relations between constraints. The use of the port abstraction graphs also reduces the number of equations that need to be solved to compact the layout.

Abstract: A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly," and non-interacting models are referred to as being "friendly.

Abstract: A system and method performs signal net matching during delay routing. The delay router employs a region search for placing pseudo pins in a search region that will satisfy specified time delay constraints for a given signal net. The search region is an octagonal region defined by Manhattan detour lengths using derived wire length constraints as applied to a bounding box for the signal net. Any sequential router can be used to search the search region for free points. A first search phase finds delay paths to all free points in the search region from an arbitrary source pin. A second search phase then searches the search region for delay paths connecting a sink pin to one of the free points. Any delay path that connects the source and sink pin through a free point in the search region satisfies the time delay constraints. Dynamical routing can be implemented during the search phases as needed.

Abstract: A method for generating hierarchical netlists for gate level or transistor level circuits having instances with properties defined by algebraic expressions. The present invention avoids duplication of instance definitions using a method of expression promotion in a computer aided design system capable of simple parameter passing, whereby expressions are replaced by tokens in the netlist, and moved up the hierarchy to a level where they can be fully evaluated. The present invention also provides a specific embodiment for implementing the expression promotion method used for netlisting.