Abstract: An electrical component model generator generates, stores, and retrieves component models in a component model library. Component models comprise property values. A property value quantifies a property. Properties are associated with a plurality of component models. The component model generator generates rules. A rule is a relationship between two or more properties. A rule applied to two or more properties associated with the component model define a property value for at least one of these properties. Properties that are not defined by rules or that have a value different from the value generated by a rule are quantified by an exception value that is input by a user. The component model generator stores the component models by storing the rules for all component models and the exception values for each component model. Generating and maintaining the component model library is facilitated by automatically applying the rules to the component model to generate some or most of the property values.

Abstract: A crosstalk analysis system that uses automatically extracted circuit timing information to calculate real-world crosstalk estimates. The crosstalk analysis system of the present invention improves the accuracy of crosstalk calculations by incorporating into the analysis automatically extracted inter-signal timing information. The present invention monitors a functional simulation run to automatically provide summary net activity time windows that are directly forward-annotated into a crosstalk analyzer. The crosstalk analyzer drastically reduces the number of crosstalk false alarms by avoiding summation of crosstalk noise between neighbor nets that switch out of phase with respect to each other.

Abstract: A computer-aided engineering (CAE) tool simulates physical floor-planning of electronic components to be placed and interconnected on both sides of a printed circuit board (PCB). Initially components are placed in a raw portion of the PCB, until an evaluator determines where to re-place selected components in refined portions on both sides of the PCB. The evaluation process is repeated until all components are selected from the raw portion and re-placed in a refined portion. During evaluation, a profile of the raw portion is generated, and the generated profile is searched for a location for placing each selected component.

Abstract: A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.

Abstract: A method is disclosed whereby systems having bidirectional and/or multiplicatively driven data paths are statically scheduled for simulation. The method flattens the netlist to convert bidirectional data flow paths into unidirectional, multiplicatively driven data paths. All drivers connected to multiplicatively driven data paths (or nets) are isolated from the net using a bus resolution block. The bus resolution block implements a resolution function which permits the system to be statically scheduled for simulation. Simulation speed is increased substantially thereby.

Abstract: A method and apparatus to enable the size reduction of geometric databases used in the analysis of integrated circuit layouts. The results of design rule analysis on the groups of polygon shapes comprising the integrated circuit layout are stored as either in-group results or override results in a dedicated result register memory. In-group results are design rule analysis results which contain only shapes contained in the group being analyzed. Override results are additional shape models produced when the spatial relationship between the shapes in the group being analyzed and shapes in lower level groups invalidate the results previously obtained for those lower level groups. The data base structure is created using a general purpose computer consisting of a CPU connected to a plurality of memories along a common data bus.

Abstract: A method for modeling traffic on a network according to a Client/Server paradigm is disclosed, The method includes the steps of interacting the model parameters from known or measured interactions between a client node running a particular application and a server node with no other activity on the network, The method is repeated for each nodal configuration and for each application until the traffic for each node-application combination has been modeled with no other load on the network.

Abstract: Disclosed is a system and method for simulating and detecting timing errors in digital circuit designs. The system consists of a logic simulator connected to various storage registers, a sequencer, and a randomizer, for simulating component functionality within the digital circuit design at sequential time increments using stored parametric data. The method includes selecting, for each component in a digital circuit design, a specific timing constraint from a range of possible timing constraint values, using a psuedo-random selection algorithm. The digital circuit is then simulated through a number of periods using this timing constraint. When an adequate number of periods have been simulated, a new set of timing constraints are selected. Timing requirement violations are detected and reported to a user.

Abstract: A LISP-based library of files of selected functionalities are preprocessed into Context files of machine-readable codes as the smallest usable modules of massive computer programs for distribution to users and for independent operation on a computer as each such functionality is required by a user. Such Context files are initially prepared after assuring that each Context file which relies on the contents of any other Context file is rendered independent by copying the dependent material into the Context file for storage and distribution therewith. At run time, each Context file is loaded into a memory segment of a computer only as needed in response to selection by a user, and as loaded into the computer for execution, clashes among names or keys associated with each newly-requested functionality in a session are resolved against the keys or names of the Context files already in memory segments of the computer.

Abstract: A hierarchical pitchmatching compactor is provided that maintains hierarchical structure, design rule correctness, and circuit integrity of a symbolic layout while globally compacting the layout without excessive computational or data handling requirements, even for layouts of substantial size. The compactor achieves this result by taking advantage of the regularity of the layout, to reduce the number of constraints in the linear programming problem to a minimum level. This minimal problem, called the minimum design, can be drastically smaller than the original minimization problem for layouts of practical interest. This technique is implemented by means of a computer program that operates on the original symbolic layout of an integrated circuit to produce an automatically compacted layout as the data output.

Abstract: Apparatus and methods for two-dimensional compaction of object collections defines an initial set of unrefined objects and an initial compaction direction. One by one, each unrefined object is taken from the unrefined object configuration and placed within a refined configuration. Both unrefined and refined configurations possess profiles along which the selected object is placed. Pruning rules select which locations to investigate more closely, by eliminating those positions that clearly do not provide compaction improvement. Various orientations and/or shapes of an object can be tried to improve the compaction or the group of objects. Once a best location for the object is found, the object is included in the refined object set, new unrefined and refined profiles are constructed, and a new unrefined object is selected to place. Once all unrefined objects have been selected and placed, the compaction process for the chosen direction has completed.

Abstract: A system and a method are described for optimizing the sequencing and time requirements for compiling large sets of source code residing in multiple hierarchical file directories using an abstracted logical description of the hierarchical file relations existing between directories. The system consists of a logic processor working in concert with input and output file registers, a match register, and an abstracted tree register for the purpose of creating a identifying, comparing, and sequencing file names in a final description of the global directory. The method iteratively identifies the primary input files and the intermediate input files for a given output file for each of a series of directories, inverts the casual relationship between the output file and its intermediary input files, and accumulates and stores these relationships in a sequential manner for subsequent use.

Abstract: A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.

Abstract: An apparatus and method for improved efficiency of operation of a circuit simulator. The simulation engine processor sends signals via flag registers to the component model processors to indicate which type of response is required from each component model. The component model processors send back only the requested response, thus minimizing processing time by avoiding generating response types that are not needed. Flexibility is enhanced by centralizing tasks in the simulation engine rather than in the component models, in order to facilitate experimentation and variation in circuit configurations without extensive modifications of component model design.

Abstract: An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes.

Abstract: A computer system and computer-implemented method for compacting the geometrical area of a hierarchical integrated circuit layout. The present invention is particularly adapted for use with layouts including over-the-cell routing (OTCR). The inventive method includes the general steps of normalizing the cells, compacting the cells, then reconstructing the layout that includes the normalized cells. More particularly, the step of normalizing the cells includes initial step of identifying an overlapping object produced from the OTCR that overlaps one of the instances. That overlapping object is then divided into an overlapping segment and a non-overlapping segment. The overlapping segment is then removed from the cell and copied into the leaf cell of the overlapped instance. The overlapping segment is defined as a special object of the cell into which it is copied.