Abstract: Some embodiments of the invention provide a method of expanding a path in a space with dimensional states. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The method identifies a first expansion for the path from a start state to a first destination state. It then specifies a first cost function that expresses the cost of the first expansion. The first cost function is defined over the destination state. The method also identifies a second expansion for the path from a first portion of the first destination state to a second destination state. From a portion of the first cost function that is defined over the first portion of the first destination state, the method computes a second cost function that specifies the cost of the second expansion.

Abstract: A technique to design deep sub-micron (DSM) integrated circuits is disclosed, in which global wire delays are minimized first, before performing logic synthesis. According to the present method, a designer performs layout of physical blocks by estimating an area for each block. After connecting the pins of the blocks with no timing constraints, each wire is assigned to a metal layer, based on length. The delay of each wire is minimized by inserting buffers at optimal distances. The blocks are then partitioned into “cores” and “shells.” The shells and cores are synthesized, and then recombined. This procedure greatly reduces the number of design iterations required to complete a design.

Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.

Abstract: Some embodiments of the invention provide a method of determining whether a set of routes can be geometrically embedded in a region according to a particular wiring model. The method identifies a congestion graph that has a set of edges, where at least two edges are neither orthogonal nor parallel. For each edge, the method identifies the set of routes that intersect the edge. It then determines whether any edge is overcongested.

Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular edge, identifies an edge-intersect cost based on a set of potential routes for the nets that intersect the particular edge, and (2) selects routes for the nets based on the computed edge-intersect costs. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. Also, different embodiments identify different edge-intersect costs.

Abstract: A method/process for repeater insertion in the absence of timing constraints. Delays are optimized for multi-receiver and multi-layer nets and can be introduced in the early steps of design planning. It serves as a tool for interconnect prediction as well as planning. In the presented formulation, no restrictions are made on where the repeaters are added or what the topology of the net is. The tabulated results demonstrate improvement (speed ups) using the method/process of the present invention. The present invention runs in linear time and achieves better results that the existing dynamic programming formulation and other published heuristics. Polarity in a circuit design is corrected by traversing the circuit and carrying backwards a cost of fixing the polarity. On a subsequent traversal, buffers inserted fix the polarity.

Abstract: Some embodiments of the invention provide a method of searching for a global path between first and second sets of routable elements in a region of a layout. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the two sets of elements. Next, it performs a path search to identify a set of path expansions between a sub-region that contains a first-set element and a sub-region that contains a second-set element. When the method performs the path search, it explores expansions along non-Manhattan directions between the sub-regions.

Abstract: A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compilable. The designer specifies both computation and communication between different hybrid code modules.

Abstract: A transmitter circuit means is arranged to provide linear amplification of non-constant envelope modulated RF signals by directly amplitude modulating the transmitter power amplifier with the amplitude component of the baseband signal. In addition, the signal to be transmitted is phase modulated by the In-phase and quadrature components of the baseband signal, and synchronization means arc provided in order to correct any time slippage between the directly applied amplitude modulation and the phase modulation. The modulation synchronisation correction contributes significantly to the linearity of the transmitter.

Abstract: An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node.

Abstract: The present invention provides a method and mechanism for optimizing the power consumption of a micro-electronic circuit. According to an embodiment, when optimizing the power consumption of a micro-electronic circuit, one or more candidates for applying one or more optimization techniques may be identified. Then, the one or more candidates may be marked with the one or more optimization techniques within the micro-electronic circuit without altering the data and/or control paths of the circuit. Then, after timing and logic optimization, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique saves power and/or satisfies the timing requirement of the circuit. Further, each power saving technique applied to the one or more candidates may be evaluated to determine whether the technique is reducible, and if so, then the technique may be reduced to determine whether such reduction improves the circuit's timing.

Abstract: A statistical approach to estimating software execution times is implemented by preparing a model of a target processing device, correlating the software to be estimated to benchmark programs used in the preparation of the model, and then applying the software to be estimated to the model. The model is developed by determining the actual execution times of the benchmark programs, determining a number of virtual instructions in the benchmark programs and determining a predictor equation that correlates the virtual instructions to the actual execution time. The predictor equation is determined by a linear regression technique that includes a correlation analysis of the virtual instructions, removal of highly correlated instructions, and a combination of stepwise linear regression and multiple linear regression to determine the predictor equation.

Abstract: A system for forming composite video images from one or more foreground images and one or more background images. In one embodiment, s sum of a suppressed foreground image signal with weight ?, with one or more selected foreground colors suppressed, and a background image signal with weight 1??? (0????1) is formed, where a and ?? may vary from pixel to pixel and with time. In another embodiment, a shadow from a selected foreground image is impressed on selected pixels of a background image. In another embodiment, foreground suppression and shadowing are combined, optionally by retrofitting, using an existing ?-mixer or a newly constructed ?-mixer. Provision of a chroma key map allows a foreground image shadow to be prescribed pixel by pixel, including a transition region in which the shadowed image slowly disappears.

Abstract: Each circuit simulation performed on unique layout of circuit devices generates a design point (DP) that includes device variable values and performance goal values. Circuit models for at least one performance goal are determined as a function of a first subset of the DPs. A performance goal value is determined for each circuit model based on the device variable values obtained from a second subset of the DPs. Errors are determined between the thus determined value of each performance goal and values of the corresponding performance goals obtained from the second subset of the DPs. Input values of device variables are processed with at least one of the circuit models having the smallest error associated therewith to determine therefor a performance goal value. A layout of the circuit devices is generated based on the input device variable values associated with at least one of the thus determined performance goals.

Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

Abstract: Some embodiments of the invention provide a method for constructing a convex polygon that encloses a set of points in a region. This method identifies a first polygon that encloses the set of points. It then identifies a second polygon that encloses the set of points. The method then specifies the convex polygon as the intersection of the first and second polygons.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. The method uses this routing graph to identify routes.

Abstract: A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to determine dimensions and locations of power grid components for each IC layer using a power grid formula, an objective for the power grid formula, a set of constraints, and a set of parameters. The method also includes processes of a power grid router, power grid verifier, and global signal router that are used iteratively with processes of the power grid planner to continually refine the dimensions and locations of the power grid components until the power grid structure meets design constraints and until global signal routing is successful on each layer of the IC.

Abstract: In a method of determining the existence of one or more conflicts in the placement or configuration of circuit objects defining a circuit, a number of constraints is defined, each of which imposes at least one limitation on at least one circuit object. A number of constraint families is then defined, each of which includes a subset of interrelated constraints. For each of a subset of the constraint families, a determination is made if a conflict exists between the constraints thereof. If not, pairs of constraint families are defined from the plurality constraint families. For each of a subset of the pairs of constraint families, a determination is made if a conflict exists between the constraints thereof. If not, the circuit objects defining the circuit are laid out subject to the constraints.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a surface. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At each intersection of the boundary of the surface and one of the vectors, the method computes a cost. Based on the computed costs, the method specifying a second PLF that is defined over the second state.