Abstract: The present disclosure relates to a system and method for use in a digital signal processing environment. Embodiments may include a programmable processor configured to execute an instruction set that includes multiply instructions and/or multiply-accumulate instructions that generate a result in carry-save format or redundant binary format. The instruction set may be executed at a single instruction, multiple data (SIMD) level.

Abstract: Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.

Abstract: Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.

Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

Abstract: A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the anticipated numbers of transfers extracted from the address calls of the stream of address calls with the number of transfers in the transfer batches of the stream of batches. Pairing a predetermined number of consecutive address calls of the stream of address calls with consecutive batches of the stream of batches based on the comparison.

Abstract: Embodiments disclosed herein provide techniques for representing a routing strip in an integrated circuit design using a digit pattern. According to certain aspects, the techniques include methods to display overlapped routing strips of an integrated circuit design when there are ten or more metal layers in the integrated circuit design. According to additional or alternative aspects, the techniques include methods to generate a texture pattern for displaying routing strips in which layer identification and layer direction of each routing strip can be easily discerned. According to further additional or alternative aspects, the techniques include methods to cause texture patterns for displaying routing strips to stagger with respect to each other when the routing strips are overlapped in a display.

Abstract: A method including receiving source code for controlling a system on a chip and correlating a datum and an instruction in the source code with a first node is provided. The method includes associating the first node with a resource used by the datum and the instruction, based on a model for the system on a chip, illustrating a link between the first node and a second node, indicative of a data dependency in the source code between the first node and the second node, and evaluating a performance of the system on a chip controlled by the source code. Also including forming an annotated source code based on the performance of the system on a chip. A system and a non-transitory, computer-readable medium including instructions to perform the method are also provided.

Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.

Abstract: A method for on-the-fly determination of leakage power and temperature of an electronic circuit design is provided. The method includes calculating a dynamic power of the electronic circuit design. The method also includes calculating a total power consumption of the electronic circuit design. The method further includes averaging the total power consumption to obtain an average total power, determining a temperature of the electronic circuit design based on the average total power, and determining a leakage power of the electronic circuit design based on the temperature. A system and a non-transitory, computer-readable medium storing computer-readable instructions to perform the above method are also provided.

Abstract: Methods and systems for code coverage mapping are provided. In one aspect, a method for code coverage mapping includes generating, by a user application executable by a computing device, a source-code handle corresponding to a transaction code. The source-code handle is communicated through an interface to a server emulating a design-under-test (DUT). Writing a value of the source-code handle to a signal in the DUT is facilitated to mark start of execution, by the user application, of one or more sequences of one or more instructions of the transaction code.

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Abstract: Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.

Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.

Abstract: A system and method are provided for reducing processing time in characterizing a programmably implemented cell. The cell is decomposed into a plurality of channel connected component portions (CCC's), each including a local output node and at least one switching device establishing a conduction channel within a channel path extending from the local output node to a power plane of the cell. A component characteristic function is generated for each CCC, which logically sums a locus of vectors for nodes electrically connected to the local output node. Each CCC's component characteristic function is expanded to form a local characteristic function relative to one or more other upstream CCC. Each local characteristic function is thereby formed exclusive of any upstream local output node electrically disconnected from its local output node. At least one feasible vector is selectively generated from the local characteristic functions according to requirements predefined for a parametric measurement.

Abstract: A method for converting a real number modeling to a synthesizable register-transfer level emulation in digital mixed signal environments is provided. The method includes verifying an input in a file including a real number modeling code and cleaning the real number modeling code in the file. The method also includes separating a clean register-transfer level code from the real number modeling code, converting the file to a cycle-driven simulation interface file, and verifying the cycle-driven simulation interface file. The method further includes converting the cycle-driven simulation interface file into a register-transfer level file suitable to perform a circuit emulation in digital mixed signal environments, and verifying that the register-transfer level file is ready to perform circuit emulation in the digital mixed signal environments. A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Abstract: An interface, a method, and a system are provided. In one or more aspects, the interface is for data transfer between simulation software and a hardware emulator associated with an integrated circuit design and includes a data producer to push a number of elements. A data element includes variable bits of data and variable bits of control information. A first-in-first-out (FIFO) receives the elements pushed by the data producer and stores pushed elements. A data consumer requests the pushed elements from the FIFO. The FIFO includes a buffer array, memory, a first push pointer and a first pop pointer associated with the buffer array, and a second push pointer and a second pop pointer associated with the memory. The buffer array stores elements in software and the memory stores elements in hardware. The interface facilitates moving a portion of hardware emulator functionalities into the simulation software and vice-versa at runtime by utilizing the FIFO.

Abstract: A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.

Abstract: The present disclosure relates to a computer-implemented method for visualizing internal instance structure and connections in a design system component. Embodiments may include receiving, using at least one processor, an IP-XACT description of one or design elements and analyzing, using the at least one processor, the IP-XACT description of the one or design elements. Embodiments may further include displaying a graphical user interface, based upon, at least in part, the IP-XACT description of one or design elements, wherein the graphical user interface is configured to display a self-organizing graphical layout including a parent component, at least one node, and at least one edge.

Abstract: The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

Abstract: A benchmark test system captures and records root, or input, behavior from a user input device as one or more time-displaced samples of input. The system also separately captures and records the canvas, or visual, behavior of a user interface in response to the captured input as a series of time-displaced image frames. The image frames are analyzed for visual prompts occurring responsive to the input, and parameters of the image frames are determined. A parametric difference between corresponding ones of the root events and canvas responses is thereby computed, in order to determine a degree of visual responsiveness for the user interface software respective to the root input.