Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation is provided. Embodiments may include providing, using one or more processors, an electronic design configured to generate one or more address sequences. Embodiments may also include applying an address noise monitor to the electronic design, wherein the address noise monitor is configured to determine address noise data, wherein the address noise data includes a measure of one or more discontinuities in the one or more address sequences. Embodiments may further include simulating the electronic design to generate one or more performance results, the one or more performance results including address noise data. Embodiments may also include generating an address noise profile, based upon, at least in part, the one or more performance results including address noise data.

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

Abstract: An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to select only the specific one or more waveforms for which the user seeks viewing of the full waveform data.

Abstract: A method for performing a regression session when testing a device under test (DUT), may include a. obtaining a coverage model of the DUT, and a verification session input file (VSIF) relating to a plurality of tests to be run on the DUT, the VSIF including an initial number of runs associated with each of the tests of the plurality of tests; b. performing a first iteration of the regression session in which each of the tests of the plurality of tests is run the initial number of runs associated with that test; c. calculating for that iteration an effectiveness grade of each run of the tests of the plurality of tests, and assigning a weight to each of the runs of the tests of the plurality of tests corresponding to the calculated effectiveness grade of that test run; an d.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.

Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.

Abstract: Electronic design automation systems, methods, and computer readable media are presented for the generation of power-related connectivity data by an analog simulator (for example, by propagating the power supply data and/or ground data through the circuit components of the analog design schematic). In some embodiments, the verification module determines consistency between different versions of power-related connectivity data, such as: (i) power-related connectivity data from the analog design schematic and (ii) power-related connectivity data from the power-related data characterizing the mixed-signal design. Such verification determines whether the mixed-signal design satisfies the low power specification as expressed in the power-related data characterizing the mixed-signal design.

Abstract: In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.

Abstract: Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

Abstract: An approach is described for implementing a GUI that provides a user interface for reviewing and correcting design rule violations within a CAD program. According to some embodiments, a user may enter a serial review process which may utilize contextual information to determine where to start that review process. Further, the serial review process may enable the user to review rule violations in an individual manner for a respective object. Furthermore, a dynamic directional violation identifier may be used to identify additional errors in the direction of movement, such as by processing a set of rules and parameters with respect to objects in the direction of movement. The serial review process and the dynamic directional violation identification may be combined in a single process such that as violations are reviewed, and corrections are attempted, they may be verified to determine if they generate additional violations.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation and returns test results and trace data. Channels of multiple buffers and associated processors implement the test operations. Compression units on each channel may compress the test and trace data to facilitate returning the results to the host device. Multiple channels may be used to compress data in parallel, thereby improving throughput.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof.

Abstract: According to certain general aspects, the present embodiments relate to methods and apparatuses for performing read and write data path training in HBMs. In accordance with some aspects, embodiments configure HBM mode registers for read and write data path training using an IEEE 1500 interface is simpler than the traditional scenario. In accordance with other aspects, the logic for performing read and write data path training is independent from normal memory access functionality in the host, capable of independently interacting with a PHY core for performing read and write data path training.

Abstract: The time to test integrated circuits is increasing as a function of the complexity of integrated circuits and processes used to fabricate the integrated circuits. Embodiments of this disclosure include systems and methods for reducing the time to integrated circuits by reducing the number of devices individually modeled. Embodiments can reduce the number of modeled devices by combining two or more devices into a single combined device that models all discrete devices, but in a reduced form.

Abstract: Systems and methods disclosed herein provide for preventing the mis-equalization of signals transmitted over short transmission channels. Embodiments of the systems and methods provide for a receiver including a digital receiver equalization circuit that selectively provides a correction signal to a DFE tap weight based on the value of the current DFE tap weight as well as the logical values of the in-phase and error data samples associated with received signal.

Abstract: Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation (“ATPG”) generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.