Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a floorplan with virtual hierarchies and figure groups for an electronic design. These techniques identify a plurality of layout circuit component designs in a layout and identify or create a figure group at a virtual hierarchy for the plurality of layout circuit component designs. The figure group can be modified into a modified figure group in response to a request for a modification of the figure group. At least one layout circuit component design of the plurality of layout circuit component designs can then be reinstalled into the modified figure group to fulfill the request for modification of the figure group.

Abstract: Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Abstract: A system and method are provided for adaptively optimized recomposition of a parts list for fabrication of an electronic circuit product. A parts list acquisition portion forms a parts list containing a plurality of constituent parts entries read from one or more predetermined sources. The parts entries are respectively identified in the parts list by different corresponding part identifiers. An optimization unit coupled to the parts list acquisition unit comparatively determines mutual matching between different parts entries based on at least one optimization parameter. The optimization unit intermediately recomposes the parts list by incorporating one or more suggested parts substitutions to adaptively consolidate mutually matched pairs of parts entries.

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Abstract: A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment's storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.

Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The method may also include running a first target node and if the first target node is proven, run at least one additional target node until all target nodes are proven.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

Abstract: A system, method, and computer program product for automatically managing control configurations in an application graphical user interface (GUI). Interface element specifications may be configured via a customized overlay file corresponding to at least one party having influence over the application controlled by the GUI, such as an application vendor, a user group, and an individual user. The overlay file is created and saved via an interface manager GUI that allows new interface elements such as toolbars and toolbar buttons to be added, and existing interface elements to be modified, but does not allow existing default interface elements to be destructively edited, only hidden or visibly disabled. The overlay file is processed during program environment startup and when user actions trigger a separate application or feature window activation or reset a particular overlay file's modifications. Compatibility with vendor-supplied default interfaces and other overlay file based customizations is maintained.

Abstract: An improved approach is provided to identifying the boundary of data encoded using additive cyclic codes. In some embodiment, the process includes determining a first calculated parity of a first bit stream window, and, second, one or more updates to the calculated parity of the bit stream window to determine the parity of the next bit stream window, where after each update to the calculated parity, the calculated parity is compared with the target parity, and matching the calculated parity to the target parity indicates a proper boundary of a bit stream window. In some embodiments, the process supports shortened cyclic codes. In some embodiments, the bit stream boundary can be identified prior to descrambling the bit stream inputs for a given bit stream window. In this way, the process can avoid unnecessarily descrambling of the bit stream windows that are not properly aligned to a bit stream boundary.

Abstract: A system and method automatically determines the physical memories inside a core or macro and their association with logical memories and their enabling signals. An integrated circuit (IC) source file that describes an integrated circuit in a hardware description language is received. The IC source file includes macros corresponding to memory. For each macro, a physical description file corresponding to the macro is generated. The description includes how the macro corresponds to the physical memory, associations of physical memories with the logical memory, enabling conditions, and data needed to test the memory.

Abstract: A system and method for generalized next-state-directed constrained random simulation may include obtaining an initial state for a finite state machine (FSM) constrained by a first Boolean random circuit; and unrolling the FSM, wherein each step of steps of the unrolling, except for a final step, is constrained by the first Boolean random circuit that defines a set of generalized cycles, and wherein the final step is constrained by a second Boolean random circuit.

Abstract: Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.

Abstract: A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a first routing trunk along channels in the circuit layout, coupling the first routing trunk to one device of the two devices, and checking that a placement of a plurality of devices and the coupling the first routing trunk to one device of the plurality of devices meet a circuit layout specification. A computer system and a non-transitory computer-readable medium storing commands to execute the above method are also provided.

Abstract: The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part, the generated change.

Abstract: A method, control apparatus, and system for re-establishing a common mode in a transmitter involve switching a driver circuit of the transmitter to a quick charge or quick discharge mode based on an output value of the transmitter. When the output later exceeds a programmable common mode voltage, the driver circuit is switched to a classical margining mode to bring the output back towards the targeted common mode voltage. The modes are switched by adjusting the number of activated pull-up and pull-down segments. More pull-up segments and less pull-down segments are activated in the quick charge mode than the classical margining mode. More pull-down segments and less pull-up segments are activated in the quick discharge mode than the classical margining mode.

Abstract: Disclosed are apparatuses and methods for implementing CMOS-based, process insensitive current reference circuit(s). An apparatus includes a constant transconductance circuitry including a first and second current mirrors and respectively generating constant currents across one or more process corners, a resistive transistor in the constant transconductance circuitry having a resistance, and a feedback circuitry coupled with the resistive transistor and the constant transconductance circuitry to form a constant current source. The apparatus may optionally include a data processing module as well as another constant transconductance circuitry, another resistive transistor, and another feedback circuitry that form another constant current source.

Abstract: A system, method, and circuits for processing a boundary scan result involve receiving the boundary scan result as input data to a comparator, and performing a comparison based on the input data and a selected reference level to form a comparison result. A capture device that stores the comparison result is set, reset or write enabled based on the comparison result and a reference value indicating which of two reference levels is the selected reference level. Additionally, a determination is made whether to change the selected reference level for a subsequent comparison based on the comparison result, the reference value, and the output of the capture device.