Abstract: A system, method, and circuits for power efficient margining in a differential output driver that includes segments connected to outputs of the driver. Each segment can be configured independently to different states by activating corresponding transistor combinations. In a transmitting state, the transistors transmit data by establishing current paths between the driver outputs and a positive supply rail or a ground rail. In a margining state, the transistors are statically configured to form current paths that differ from those of the transmitting state, such that the segment contributes substantially a same differential impedance between the driver outputs as would be contributed by the segment when in the transmitting state, while contributing a different common mode impedance than in the transmitting state. The current paths of the margining state extend through transistors that transmit data in the transmitting state.

Abstract: Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection.

Abstract: A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.

Abstract: A system, method, and computer program product for determining whether a design for a circuit meets design specifications, to facilitate the provision of a manufacturable description of the circuit. A computer-operated circuit simulation tool reads the design for the circuit and a power specification, and selectively internally creates a network connection and inserts a corresponding connect module in the design, for at least one circuit block having an unsupported signal declared in the power specification. Typically such a circuit block will be an analog block, whether an original analog block or an analog representation of a digital block, and may involve electrical or wreal signal interactions. The simulation tool performs a mixed-signal simulation of the design. Embodiments tangibly output a verification determination from a comparison of the simulated design performance results and the design specifications in order to provide the manufacturable description of the circuit.

Abstract: Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.

Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.

Abstract: A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and identify necessary communications between the processors relating to synchronization points between them. The method may further include automatically generating a test that includes a plurality of actions performed by some or all of the processors in compliance with the legal order.

Abstract: Aspects of the present invention provide a system and method for a user of an event-driven simulator to specify breakpoint conditions in kernel modules, startup processes, shared libraries, and other automatically loaded software elements before the target environment is initialized. The virtual platform detects specified breakpoints when a file is loaded onto a virtual platform debugger during startup of the environment or initialization of the relevant processes. The virtual platform debugger may scan for specified breakpoints in all loaded source code files, in only those source code files that are automatically loaded, or in only those source code files specified by the designer as modified.

Abstract: Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate adjustment of parameters of instances of programmable cells in the chain.

Abstract: The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without receiving authorization from a server computing device and transmitting the implemented change to the electronic circuit design to the server computing device.

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design including a first net and a second net. The method may include identifying a shortest path between the first net and the second net and determining at least one common shape associated with the shortest path. The method may also include identifying one or more adjacent shapes to the at least one common shape and identifying at least one fork associated with each of the one or more connectivity reference points. The method may further include analyzing an intermediate fork of the at least one fork to identify an electrical short associated with the electronic design.

Abstract: Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design objects may also be displayed according to a type of design feature represented by the design object. For example, the embodiments described herein may represent a “port” as having a shape and size that comports with the eccentricities of both electrical and photonic designs. A port may be a hierarchical connection element in the database allowing the logical and physical connection between an instance and the geometries in the corresponding instance master.

Abstract: Disclosed are mechanisms for implementing three-dimensional operations for electronic circuit designs. These mechanisms identify a cross-layer layout portion by identifying a first electronic design as an editable layout portion and a second electronic design as a selectable and non-editable layout portion in a single window, determine a ruler by identifying or generating the ruler for a three-dimensional operation across the first electronic design and the second electronic design on different layers, identify one or more starting targets and one or more end targets within an aperture at least by determining the one or more starting targets and one or more end targets based in part or in whole upon a location of the aperture and the one or more rulers, and perform the three-dimensional operation at least by manipulating a plurality of shapes in the cross-layer layout portion based in part or in whole upon the one or more rulers.

Abstract: Disclosed are techniques for model-based electronic design implementation with a hybrid solver. These techniques generate an extruded via from a linkage node to a reference metal plane that is added to an analysis model for at least a portion of an electronic design. The analysis model for the at least the portion is generated at least by re-establishing interconnection between the at least the portion and a linkage circuit element with the extruded via. At least the portion of the electronic design may further be implemented using the analysis or simulation results that are generated by using the hybrid solver on the model, without using three-dimensional solvers, for a three-dimensional model of the electronic design.

Abstract: Disclosed are techniques for enhancing formal verification with counter acceleration for electronic designs. These techniques identify at least a portion of an electronic design including a counter having a current counter value and intercept next counter values transmitted to the counter with a counter abstraction module. These techniques further determine whether to accelerate the counter from the current counter value to an engine synthesized next counter value, rather than to an original next counter value based at least in part on a set of critical values. The counter is accelerated from the current counter value to the engine synthesized next counter value when the counter abstraction module determines to accelerate the counter.

Abstract: Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.

Abstract: Disclosed are techniques for implementing trace warping for electronic designs. These techniques identify a portion of an electronic design including a set of signals of interest corresponding to a plurality of simulation combinations over a range of clock cycles in a trace display. A pair of matching simulation combinations is identified from one or more pairs of matching simulation combinations for the set of signals of interest; and a first clock cycle and a second clock cycle corresponding to the pair of matching simulation combinations are identified in the range of clock cycles. A plurality of clock cycles between the first clock cycle and the second clock cycle can be compressed in the trace display.

Abstract: Electronic design automation systems and methods are presented for top-down timing budget flow in master-clone scenarios. In some embodiments, different instances of a master-clone block within an integrated circuit design are associated with different constraint files. The different constraint files are based on the different connections of each instance with elements of the integrated circuit design as well as the shared structure of the master-clone block. A top-down timing budget flow may then be generated based on the differing constraint files, and the integrated circuit design may be modified based on this analysis prior to generation of physical devices based on the design.

Abstract: Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.

Abstract: A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode process with error correction. In some embodiments 26 data bits from two 13-bit word are encoded into a 40-bit encoded word. Bits of two or more encoded words may be interleaved for transmission, or multiple copies of encoded words sent. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may also implement the disclosed encoding/decoding for interconnections between emulation chips.