Abstract: The present disclosure relates to a computer-implemented method for generating an electronic design automation differences report is provided. The method may include modifying instructions configured to generate a report of an electronic design and generating a data file based upon, at least in part, the modified instructions. The method may further include converting the data file to a second data file using, at least in part, the template. The method may also include generating a report viewer, based upon, at least in part, the second data file.

Abstract: A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs an arithmetic operation or a complex logical operation of the electronic circuit design, and a set of flag registers that contains a conditional value for enabling the arithmetic logic unit.

Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

Abstract: A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment. Each timing skew factor is generated based adaptively on the output samples for a selective combination of segments including at least one preceding and at least one succeeding sample segment. A plurality of timing control units respectively coupled to the ADC channels adjust time delays for the sampling clock within respective sample segments responsive to the timing skew factors, thereby substantially aligning the sample segments with the sampling clock.

Abstract: Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.

Abstract: A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks. One aspect identifies an area in an electronic design and a track pattern associated with the area, identifies active tracks in the track pattern, and creates spacetiles with the active tracks. This aspect uses area-based search probes based on spacetiles to find viable implementation solutions to implement the area in the electronic design. Another aspect identifies a tracked area associated with a track pattern and a trackless area and use spacetile(s) and a via spacetile layer to transition between the tracked area and the trackless area for implementation of the electronic design in the tracked or the trackless area of the electronic design.

Abstract: A system, method, and computer program product is disclosed that for debugging errors in software code. According to some approaches, techniques are provided for performing on-the-fly switching from compiled to interpretive debugging for a software program. The test starts with compiled code, and when it needs to stop for debugging, the debugging occurs in interpretive mode. Once debugging has concluded, the execution can switch back to compiled mode. In this way, the debugging activities can achieve the speed and efficiency of using compiled optimized executables, while still being able to allow debugging without performing any recompilations.

Abstract: A system and method provide semiconductor fabrication mask creation techniques that align the device features patterned with a first core mask with one or more pad features patterned with a subsequent pad mask. Shapes representing the pad features may be included in the core mask by reducing on all sides, the shape of the pad feature in the core mask by the width of the spacer material. A pad mask then may be created to include a shape of the pad feature that may overlap a portion of the spacer material pattern created by the shape of the pad feature in the core mask. Data sets may be generated from a circuit design to create the masks that may be fabricated with the described techniques.

Abstract: An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.

Abstract: A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.

Abstract: The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit. The method may further include generating one or more faults in a cone of influence of an assertion and placing a constraint configured to model an original design for the one or more faults. The method may also include initiating formal verification on the electronic design while ignoring all electronic design constraints. The method may further include determining if the assertion is passing, wherein determining includes activating an original design for a subset of faults. If the assertion is passing, the method may include activating a single fault from the subset, determining if the assertion is passing and if the assertion does pass, deleting the single fault from the subset.

Abstract: Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.

Abstract: Various aspects described herein identify an area in an electronic design, identify a set of track patterns or track pattern groups for the area based on a set of criteria, and iteratively implement the electronic design in the area using at least some of the set of track patterns. These aspects may dynamically or iteratively update the assignment of one or more track patterns to the region based at least in part upon the implementation of the electronic design in the area or one or more attributes of one or more other areas on the same layer as the current layer of interest or on one or more different layers.

Abstract: Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Abstract: The present invention provides for a method and circuit of an integrated circuit (IC) having dual row input/output (I/O). The circuit having a plurality of dual I/Os including an upper row of I/O and a lower row of I/O, with logic arranged in communication between the upper and the lower rows of the dual row I/O. The connectivity with the logic circuits of the present invention therefore provides for improving reliability and performance through more similar and uniform pathway connections. Advantageously, the present invention also provides for the reallocation of valuable footprint space as the logic is embedded within the dual row I/O thereby creating additional footprint space for further performance and other beneficial gain where interconnects as between the physical layer (PHY) logic and I/O cells are generally similar in length.

Abstract: Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Abstract: A multimode physical (MMP) layer circuit for physical (PHY) layer handling of signals transported over a high-definition multimedia interface (HDMI) cable in a home multimedia network, wherein the signals are compliant with at least two different PHY layer modes. The MMP layer circuits comprises a plurality of PHY transceivers respectively coupled to a plurality of TP channels of the HDMI cable through a HDMI connector, wherein each PHY transceiver of the plurality of PHY transceivers handles signals transported over its respective TP channel according to a PHY layer mode of the transported signals; and a controller is coupled to the HDMI connector and to each of the plurality of PHY transceivers, the controller recognizes the PHY layer mode of signals transported over each of the plurality of TP channels and sets each of the plurality of PHY transceivers according to the recognized PHY layer mode.