Abstract: Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

Abstract: A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

Abstract: An electronic circuit design system for generating a programmable set of figures of an electronic circuit layout is provided. The system includes a non-transitory machine-readable layout database storing an electronic circuit layout of an electronic circuit design. The system further includes a circuit designer interface for viewing representations of the electronic circuit layout on a display unit and receiving inputs by one or more electronic circuit designers. The system further includes a processor configured to generate a figure group in the electronic circuit layout of the electronic circuit design; generate one or more templates comprising one or more parameters and a programming language code; and generate a parameterized figure group by associating the one or more templates to the figure group.

Abstract: A method for automatically verifying validity of application of a refinement rule includes calculating a set of values that characterize a hierarchy of elements of the emulation. A currently calculated value for a first element at a first level of the hierarchy is compared with a previously calculated value that characterized the first element at a previous time. If the currently calculated value is the same as the previously calculated value, application of the refinement rule is determined to be valid for unnamed entities of the first element. If the currently calculated value is different from the previously calculated value, each currently calculated value that characterizes a lower level element at a lower level of the hierarchy is compared with a corresponding previously calculated value to identify a change and it is determined whether the change invalidates application of the refinement rule to an unnamed entity of the emulation.

Abstract: A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.

Abstract: Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out (“FIFO”) shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.

Abstract: A circuit and method for controlling a pre-cursor coefficient in an equalizer of a transmitter device. An input signal from the transmitter is converted into a data signal that includes data symbols transmitted in successive unit intervals. An error signal is formed by comparing the input signal to a threshold value. A determination is made whether to adjust the pre-cursor coefficient, by correlating a sample of the error signal with samples of the data signal from one unit interval earlier and two unit intervals earlier.

Abstract: Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.

Abstract: Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Abstract: The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations.

Abstract: Disclosed are methods and apparatus for implementing system simulation. The method includes generating a high-order equation based on a transfer function that represents characteristics of at least one frequency-domain component in a circuit; converting the high-order equation into a state equation comprising a series of state variables, wherein the high-order equation and the state equation have corresponding coefficients for each order and state variable, and the coefficients of the state equation have a first dynamic range; and normalizing the coefficients for the state variables by adjusting each state variable with a corresponding factor to obtain a normalized state equation having normalized coefficients, wherein the normalized coefficients of the normalized state equation have a second dynamic range smaller than the first dynamic range. The method and apparatus improve accuracy of analyses for the system.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: Various embodiments are to a simulation platform with dynamic device model libraries and the implementation therefor. The simulation platform includes one or more servers hosting thereupon a database management system, a simulation frontend, and a simulation backend. The simulation frontend includes or is operatively coupled to one or more electronic design databases managed by a database management system, stored in a persistent storage device, and including design data in one or more domains across one or more design fabrics. The simulation backend includes or is operatively coupled to one or more simulators that perform simulations, analyzes, and/or optimizations for an electronic design by obtaining simulation inputs that are appended to the one or more electronic design databases or are stored in one or more separate data structures that are co-managed by the database management system.

Abstract: A method for debugging a system on chip (SoC) under test, the method may include executing a test code on the SoC, the test code designed to invoke a plurality of actions; recording output data from the SoC resulting from the executed test code; linking between actions detected in the recorded output data and actions of the plurality of actions of the test code by identifying a start and an end times of each of the detected actions in the recorded output data, and associating the identified start and end times with a start and an end times of actions of the plurality of actions of the test code; and causing display, via a graphical user interface, of a waveform representation of the detected actions over time, a representation of the test code and a representation of the output log.

Abstract: Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.

Abstract: The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

Abstract: The present disclosure relates to a system and method for fluid parameterized cell (Pcell) evaluation. Embodiments may include displaying a fluid Pcell in a first format. Embodiments may further include identifying a first state in a fluid Pcell evaluation code. In some embodiments, the first state may indicate that alterations are being made to the fluid Pcell. Embodiments may also include displaying instances of the fluid Pcell in a second format based upon, at least in part, identifying the first state in the fluid Pcell evaluation code. Embodiments may further include identifying a second state in the fluid Pcell evaluation code. In some embodiments, the second state may indicate the completion of the alterations to the fluid Pcell. Embodiments may also include displaying a final instance of the fluid Pcell in the first format based upon, at least in part, identifying the second state in the fluid Pcell evaluation code.