Abstract: In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.

Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.

Abstract: A system and method in accordance with the present invention provides for a solution benefiting from providing for non-duplicative access to data located in a system memory via the alignment of transaction sub-command breaking points with memory burst boundaries associated with the system memory, by creating a plurality of sub-commands for a transaction each having breaking points, identifying a plurality of memory burst boundaries for the system memory each having burst boundary points, and aligning a plurality of breaking points with a plurality of burst boundary points to provide single access to data located in the system memory.

Abstract: A computer-implemented method and system for debugging a program is disclosed. The method may include obtaining data on inter-component calls of a call chain of an execution run of the program between segments of Multilanguage software components of the program, the data relating to the identity of the Multilanguage software components in which these segments are included and an order in which the segments are called in the call chain. The method may further include obtaining a user selection relating to one of the segments of the Multilanguage software components that were called in the call chain. The method may also include invoking a debugger designed for debugging the software component of the Multilanguage software components that includes the selected segment and displaying a user interface of that debugger on a display device.

Abstract: A computer implemented method for debugging of a program may include parsing a code segment of the program, the code segment invoking one or a plurality of execution events during an execution of the program to derive a plurality of questions, each relating to an execution event of said one or a plurality of execution events, based on the parsing of the code segment and on information recorded during the execution of the program. The method may also include selecting one of the questions as a current question. The method may further include presenting in a user interface the current question with one or a plurality of causes related to the current question, and one or a plurality of other questions of said one or a plurality of questions for selection by the user.

Abstract: A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software debugging tool of a step of the operation as a event of interest, collecting data related to that event of interest. A unique identifier is assigned to the collected data. Access to the collected data is enabled for a second user of the software debugging tool.

Abstract: A computer-implemented method, system and computer program product for visualizing derived layer shapes of an integrated circuit design are disclosed. The computer-implemented method, system and computer program product include visualizing the derived layer shapes on a layout canvas; providing a step by step process for visualizing each derived layer shape as each derived layer shape is generated; and providing a hierarchy of intermediate derived layers based upon the step by step process.

Abstract: A method is provided to evaluate user interaction with a computer user interface (UI) comprising: receiving a property definition that identifies at least one relationship among prescribed string patterns that correspond to one or more UI events; receiving a log file in a computer readable storage device that includes a plurality of respective chunks of information; determining whether the respective chunks of information within the log file includes a respective string pattern that matches at least one of the prescribed string patterns; configuring a processor to produce an indication of whether the property is satisfied based upon the string pattern matching determinations.

Abstract: An apparatus and method for detecting memory access violations in simulations is disclosed herein. A detection tool is designed to automatically perform a violation check for each memory read or write operation simulated in a modeled system. The detection tool is capable of handling a modeled system including one or more memories and/or one or more processors.

Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.

Abstract: A system and method for evaluating a design layout by identifying squish patterns for configurations of shapes in windows defined for anchors in the layout, identifying deltas between edges of elements in the windows and reducing each delta to a single width are described. Identified squish patterns may be compared to known patterns to determine if the squish pattern is a known good or bad pattern. A squish pattern may be represented by a pixel map such that each pixel is a reduced delta in the window and each pixel has a bit representing a layer in a multi-layer layout. A plurality of stored squish patterns may be searched to identify a matching squish pattern, a specific configuration of the squish pattern, or configurations of the squish pattern having deltas within a specified range.

Abstract: In one embodiment of the invention, a method for displaying and analyzing a clock gate tree topology is disclosed. The method includes displaying a bounding box of each flip-flop cluster in the floor plan of the integrated circuit; and for each flip-flop cluster, calculating the coordinates for a center of mass of the flip-flop cluster, displaying the position of the clock gate driving the flip-flops in the flip-flop cluster with respect to the center of mass of the flip-flop cluster, displaying first air lines from the enable signal gate to the clock gate with a first color, and displaying second air lines from the clock gate to the center of mass of the flip-flop cluster with a second color differing from the first color.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.

Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Abstract: A system and method are provided for ensuring reliable data transfers by automatically recovering from un-correctable errors detected in data traversing throughout a system and being retrieved from an unreliable intermediate data buffer between a first memory and a secondary slower memory. Additionally, measures to compensate for the use of unreliable or error-prone components and interconnects, such as, for example, SRAM memory as a temporary buffer are provided. Further, measures to detect and correct errors—whatever the type—injected or occurring at any stage throughout traversal of the system are provided.

Abstract: An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. An ordered metric allocates output variance contributions for each input mismatch parameter in a linear model. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions. Additional sensitivity analysis can derive a final accurate linear contribution. Embodiments can reduce required simulations by a factor of ten.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.

Abstract: A system and method are provided for level shifting signals generated by an electronic circuit with selectively controlled frequency response. A first circuit portion defines a primary path for a signal within an upper region of a predefined signal frequency range, and includes a first capacitor unit establishing a voltage level shift for a signal passing therethrough. A second circuit portion selectively defines a secondary path bypassing the primary path for a signal within a lower region of the predefined signal frequency range, and includes a switched capacitive section disposed in parallel across the first capacitor unit to establish a voltage level shift for the signal passing therethrough. A second capacitor unit charges substantially to a predetermined shift voltage in a charging phase and couples to the first capacitor unit during a transfer phase. An attenuation adjust unit adjustably augments a parasitic capacitance of the first or second circuit portion.