Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing multi-scenario physically-aware design of electronic circuit design(s). In some embodiments, the method captures layout dependent effect(s) when a critical component instance, which corresponds to multiple candidate configurations, is being created in a physical design to enable a designer to create partial layout(s) from layout alternative(s) and to extract parameter(s) from the partial layout(s) in different layout contexts. The method may extract parasitics between components and analyzes impact(s) of layout dependent effect(s) on an electronic design by performing simulation(s) with layout dependent effect(s) in the schematic domain and may perform some partial routing based on some routing style(s) in each of the different layout contexts to generate just enough interconnects that may affect the electronic design.

Abstract: An adjustable gain amplifier system having cleanly adjustable and stable linearized gain is provided for amplifying an input signal. The system generally comprises a main amplifier and a linearized transconductance amplifier coupled thereto, which generates an amplified current signal in response to the input signal according to a variably defined transconductance factor. The linearized transconductance amplifier includes a linearized transconductance portion and a translinear current amplifier portion coupled thereto. The linearized transconductance portion generates an intermediate current signal based upon a voltage of the input signal, and forms an unswitched resistor-based conduction path for that intermediate current signal. The translinear current amplifier portion forms a translinear loop section for amplifying the intermediate current signal to generate the amplified current signal.

Abstract: The present disclosure relates to a computer-implemented method for electronic design visualization. The method may include providing, using at least one computing device, an electronic design and identifying a plurality of power domains associated with the electronic design. The method may further include associating, using the at least one computing device, at least two of the plurality of power domains with a particular group and displaying one or more of the plurality of power domains in a hierarchical manner.

Abstract: A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Abstract: A method is provided for use during static timing analysis of an integrated circuit design to produce an equivalent waveform model, the method comprising: using an analog model of the inner component, to simulate an inner component to produce multiple analog simulation output characterization waveforms as a function of multiple input waveforms used to characterize the design cell; using the analog model of the inner component to simulate the inner component to produce an analog simulation output waveform as a function of the complex waveform; and producing the equivalent waveform model as a function of the multiple analog simulation output characterization waveforms and the analog simulation output waveform.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Abstract: An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.

Abstract: Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller and therefore easier to understand and debug.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.

Abstract: A method is provided to align poly features within chain sets in an integrated circuit layout design stored in a non-transitory computer readable storage device comprising: vertically aligning a first poly feature of a first pcell instance in a first chain set with a second poly feature of a second pcell instance in a second chain set; configuring a computer to, starting with the aligned first and second poly features, successively determine multiple changed poly feature spacing values associated with at least one of the first and second pcell instances to align successive poly features in chain order in a first horizontal direction; and assigning respective determined changed poly feature spacing values to their associated first or second pcell instances.

Abstract: An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.

Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: Disclosed is an improved method, system, and computer program product for implementing flexible models to perform efficient prototyping of clock structures in electronic designs, which allows for very efficient analysis of the electronic designs. Some approaches pertain to usage of the flexible abstraction models that also include clock abstractions to more efficiently perform analysis upon the electronic designs. This allows greater analysis efficiency with regards to timing analysis and physical analysis.

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract: A system and method are provided for combined generation of I and Q signal references according to a periodic input signal and selective phase interpolation of an output signal with reference thereto. A ring oscillator portion generates an oscillator signal, and includes a plurality of delay stages interconnected in cascade to collectively execute an odd number of signal state inversions within a closed loop. The delay stages establish at respective nodes defined therebetween correspondingly delayed oscillator signal versions, successively shifted in phase by a predetermined phase difference. A signal injection portion selectively applies to at least one node of the ring oscillator portion a current bias according to the periodic input signal, and selectively adjusts each current bias in amplitude. The oscillator signal is thereby frequency locked to the periodic input signal, defining I/Q references with respect to the delayed oscillator signal version established at the current biased node.