Abstract: Disclosed are methods, systems, and articles of manufacture for using pattern matching with an integrated circuit layout including recognizing shapes within the IC layout, identifying features for the shapes, and extracting situations for the respective features. The method may further include simulating the situations to determine a set of situations for modification based on an OPC requirement, modifying the set of situations to improve satisfaction of the OPC requirement, and reintegrating the modified set of situations into the IC layout. The method may also include simulating a subset of the extracted situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. The method may also include removing overlap from a window based on the situations extracted for the window, calculating a density for each of the situations, and calculating a density for the window based on the density.

Abstract: An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.

Abstract: The present disclosure teaches a system and method for register-transfer level (RTL) design checking for exploring mismatches and ambiguous language semantics that occur during the simulation and synthesis phases of the circuit design. In particular, the present disclosure utilizes identified patterns of design violations that occur as a result of these mismatches to create rule objects. The rule objects are then used to identify circuit design violations relating to mismatches between designer intent and ambiguous language. The rule objects are also categorized into different categories so as aid in the analysis of design rule violations and to identify the major impacts to the design qualities and to provide a confidence level of the overall design quality.

Abstract: Various processes or modules described herein enable the schematic design tools to obtain physical data of a physical design and to perform one or more simulations in the schematic domain with such physical data such that the schematic design tools are made electrically aware of the physical data. Various types of data in the physical domain may be transferred to the schematic domain for the performance of one or more schematic simulations with the transferred data. The schematic designs are thus made electrically aware of such data from the physical domain and may incorporate any layout induced effects early in the schematic design stage or even at the time a schematic instance of a physical module is to be created in the schematic domain.

Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: A method and system in accordance with the present invention provides for a method and circuit for oversampling using a delay element in which input clock signals and input data signals are affected by phase and time delays to provide for the circuit generating samples providing a greater granularity of detail over a period, thereby reducing error probabilities.

Abstract: Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied.

Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

Abstract: Various embodiments of the present invention are generally directed to a method and system for functionally verifying a network device design programmed into a hardware logic verification system. The method and system encapsulates and de-encapsulates test patterns generated by a tester application into and out of network packets, which are further encapsulated into and de-encapsulated from enclosing data packets for fast and efficient delivery to the network device. Such method and system decreases functional verification times for a network device DUT while requiring little to no modification of existing tester applications and functional verification hardware.

Abstract: The present patent document relates a method and apparatus for compressing probe system data in hardware functional verification systems used to verify user logic designs. Such systems can create large amounts of data every data cycle, which can include many bits that do not toggle from one cycle to the next. Compressing such data is possible by arranging the data in bytes and determining which bytes contain bits that have changed. A status byte may be generated that conveys which bytes contain changed bits. Together the status byte and only the bytes that contain changed bits are transmitted to a host workstation, saving bandwidth on the communication interface.

Abstract: Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Abstract: The present disclosure relates to a method for Analog-to-Digital Converter Based Decision Feedback Equalization. The method may include providing an integrated circuit including a SERDES circuitry having a transmit circuitry and a receiver circuitry and receiving a high-speed data stream at the receiver circuitry. The method may also include converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter and providing the digital signal to a digital decision feedback equalization circuitry via the successive approximation analog-to-digital converter. The method may also include generating an output signal at a phase locked loop and receiving the output signal at a multi-loop clock and data recovery circuitry.

Abstract: The present disclosure relates to a method for analog-to-digital converter based decision feedback equalization. The method may include providing an integrated circuit including a SerDes circuitry having a transmit circuitry and a receiver circuitry. The method may further include receiving a high-speed data stream at the receiver circuitry and converting the high-speed data stream to a digital signal using a successive approximation analog-to-digital converter. The method may also include providing the digital signal to a digital decision feedback equalization circuitry via the successive approximation analog-to-digital converter.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.