Abstract: Systems and methods for generating an image are provided. These systems and methods include generating multiple light beams from a light source by controlling at least one parameter of the light source to be different among each of the multiple light beams. The systems and methods further include forming multiple light patterns of circuit structures that are separated in frequency by directing each of the light beams at a mask of circuit features. The systems and methods, when used in lithography for example, further include directing each of the light patterns toward a silicon substrate. The silicon substrate includes a silicon wafer having a surface at least partially covered with at least one of a photoresist material and a reversible contrast enhancement material (R-CEM).

Abstract: A method for displaying layout-fixing hints for resolving color-seeding violations in an IC design layout. The method receives a set of error paths within a disjoint set of shapes. For each error path, the method performs an analysis on the error path to identify a set of layout-fixing hints that eliminates the color-seeding violation on the error path and does not introduce any new color-seeding violation. The method displays the set of identified hints for each error path in order to aid a user to resolve the color-seeding violations. The method displays each identified layout-fixing hint as a set of moving instructions. The set of moving instructions provides a set of indications of a distance by which a shape or an edge of the shape needs to be moved in order to resolve a color-seeding violation.

Abstract: In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract: A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.

Abstract: The present disclosure relates to a computer-implemented method for abstract software performance profiling. The method may include providing, using a computing device, a virtual run-time stack associated with a software performance profile. The method may further include generating, using the computing device, at least one abstract tag associated with the virtual run-time stack. The method may also include performing, using the computing device, at least one operation on the virtual run-time stack, the at least one operation including, at least in part, the at least one abstract tag.

Abstract: A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

Abstract: A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed cursor, and wherein no labels are displayed outside of the zone.

Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Abstract: Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.

Abstract: A circuit design system generates a circuit variant by relocating one or more circuit elements through a user move action on a user interface. When the user move action results in the circuit element traversing a circuit domain boundary, the design system performs one or more operations to form the circuit variant having its initial connectivity with the relocated circuit element without any other user action on the user interface than the user move action. Further, in response to no other action on the user interface than the user move action, analysis tools and reports are initiated so that rapid evaluation of circuit variants may be implemented.

Abstract: Searching and/or replacing graphical objects of a design using a computer system. In one aspect of the inventions, a method includes searching a graphical design for all matching instances of graphical objects that match a search pattern. A graphical replacement pattern is received and caused to be displayed based on user input, and the matching instances in the graphical design are replaced with the graphical replacement pattern. At least one result of the replacement of the matching instances is caused to be displayed on a display device.

Abstract: An automated system-on-chip (SOC) hardware and software cogeneration design flow allows an SOC designer, using a single source description for any platform-independent combination of reused or new IP blocks, to produce a configured hardware description language (HDL) description of the circuitry necessary to implement the SOC, while at the same time producing the development tools (e.g., compilers, assemblers, debuggers, simulator, software support libraries, reset sequences, etc.) used to generate the SOC software and the diagnostics environment used to verify the SOC.

Abstract: Searching for graphical objects of a design using a computer system. In one aspect of the inventions, a method includes defining a graphical search pattern based on input received from a user in a graphical interface displayed on a display device, where the search pattern is a graphical object and is defined with a plurality of types of characteristics. The graphical design is searched for all matching instances of graphical objects in the design that match the search pattern and match the characteristics specified by the search pattern. At least one of the matching instances is caused to be displayed on the display device as a result of the searching.

Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract: Disclosed is a method and system for visualizing pin access locations on an integrated circuit design. Visual feedback is provided to a user that is attempting to connect a wire or a via to a pin structure polygon on the integrated circuit design. The visual feedback comprises any visual cue that provides an indication of a legal location to access the pin.