Abstract: A dust collection device includes: an air inlet channel, a dust settling channel extending along a preset path, an airflow rotation channel surrounding the settling channel, an air outlet channel and a collection chamber, where one end of the airflow rotation channel is communicated with the dust settling channel, and the other end of the airflow rotation channel is communicated with the air outlet channel; an upstream end of the dust settling channel is communicated with the air inlet channel, and a downstream end of the dust settling channel is communicated with the collection chamber; and the height of the dust settling channel gradually decreases in an extension direction of the preset path. Dust in the airflow rotation channel can easily settle under the action of a centrifugal force when moving along the airflow rotation channel.

Abstract: A gas circulation apparatus is applied to a pneumatic apparatus including a solenoid valve apparatus and a cylinder apparatus, and is connected in series between the solenoid valve apparatus and the cylinder apparatus. The gas circulation apparatus includes a valve core structure, a first circulation cavity, and a second circulation cavity. The valve core structure is configured to move in a first direction, so that compressed gas discharged from a first cylinder cavity of the cylinder apparatus and passing through the solenoid valve apparatus is collected and stored by the first circulation cavity, and a second cylinder cavity of the cylinder apparatus is supplied with compressed gas stored in the second circulation cavity together with the compressed gas supplied from the solenoid valve apparatus.

Abstract: A semiconductor structure includes a substrate with a plurality of word line trenches and source/drain regions each adjacent to each word line trench; a word line located in the word line trench, which includes a first conductive layer located at a bottom of the word line trench, a single junction layer and a second conductive layer stacked in sequence, in which a projection of the word line on a sidewall of the word line trench and the projection of the source/drain region on the sidewall of the word line trench have an overlapping region with a preset height, and when a voltage applied to the word line is less than a preset voltage, a resistance of the single junction layer is greater than the preset resistance, to make the first conductive layer and the second conductive layer disconnected.

Abstract: A wiring quality test method includes the following: a respective wiring result topological structure and a respective expected topological structure corresponding to each signal to be tested in a set of signals to be tested are determined based on a wiring layout; for each signal to be tested, the wiring result topological structure is compared with the expected topological structure, to obtain a topological structure comparison result corresponding to the signal to be tested; in response to determining that the topological structure comparison result is greater than a preset threshold, it is determined a test result indicating that wiring for the signal to be tested is inappropriate; and a quality test report is generated based on test results of the signals to be tested.

Abstract: A semiconductor structure includes a substrate, a via, a conductive pillar, and a core layer. The via is located in the substrate. The conductive pillar is located in the via, and the conductive pillar is provided with a groove extended inwards from an upper surface of the conductive pillar. The core layer is located in the groove, a Young modulus of the core layer is less than that of the conductive pillar.

Abstract: Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.

Abstract: The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.

Abstract: A wafer cleaning apparatus includes: a brush, configured to wash a surface to be cleaned of a wafer; a base for carrying the brush, the base having at least one conductive disk, a disk surface of the conductive disk being parallel to the surface to be cleaned, and the base being able to rotate around an axis of the base; and a magnetic field generation structure configured to emit, to the conductive disk, a magnetic field perpendicular to the disk surface of the conductive disk, so that an induced electric field is generated in the conductive disk during the rotation of the base. The quality of wafer cleaning and the yield of wafer products can be improved.

Abstract: The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M?1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; an isolation structure, formed in the substrate; a word line (WL), a part of the WL being located in the isolation structure; and a conductive portion, located at a bottom of the isolation structure.

Abstract: A method for temperature control includes: acquiring the present temperature of a reaction window in a process chamber of a semiconductor machine; comparing the present temperature with the preset temperature to acquire a comparison result; and adjusting the exhaust amount of an exhaust passage of the process chamber based on the comparison result to control the temperature of the reaction window.

Abstract: A word line driver circuit may at least include multiple word line drivers, each of which including a PMOS transistor and at least one NMOS transistor. The multiple word line drivers include multiple PMOS transistors and multiple NMOS transistors. The multiple PMOS transistors are arranged side by side, and in an arrangement direction of the multiple PMOS transistors, a part of the multiple NMOS transistors are located on a side of the multiple PMOS transistors, and another part of the NMOS transistors are located on another side of the multiple PMOS transistors.

Abstract: A leak detection cart at least includes a cart body and a fixing clip arranged on the cart body. The cart body is configured to place a component to be leak-detected, and the fixing clip is configured to fix the cart body and the component to be leak-detected. The cart body is provided with a leak detection hole, and the leak detection hole is located in a projection region of the component to be leak-detected on the cart body, and is configured to implement a leak detection for the component to be leak-detected.

Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Abstract: A latch circuit includes a latch module, a set control module, a reset control module and a clock module, wherein the latch module is employed for latching data input by a data module, the set control module is employed for controlling the latch module to output a high-level signal, the reset control module is employed for controlling the latch module to output a low-level signal, and the clock module is employed for providing a readout clock signal to the latch module.

Abstract: The present application discloses a diffusion furnace, including: a furnace tube structure including a furnace tube body and a furnace bottom, a bottom of the furnace tube body being connected to the furnace bottom to form a reaction chamber; and a carrying structure including a pedestal and a plurality of cassettes disposed on the pedestal, the pedestal being disposed on the furnace bottom. By disposing the plurality of the cassettes, a height of the furnace tube body can be decreased and a width of the furnace tube body can be increased, thus enlarging a space of equipment repair and maintenance, which is favorable for the repair and maintenance of the equipment.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

Abstract: A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit.

Abstract: A semiconductor structure includes: a base; a first conductive layer, having a portion located within the base and a remaining portion protruding above the base; a barrier layer on the base and at least on a sidewall of the first conductive layer protruding from the base; a dielectric layer on the barrier layer; and a second conductive layer penetrating the dielectric layer and the barrier layer, in contact with the sidewall of the barrier layer, and in contact with at least a portion of the upper surface of the first conductive layer.