Patents Assigned to Chartered Semiconductor Manufacturing Ltd.
  • Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects
    Patent number: 7601607
    Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: October 13, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Wuping Liu, Raymond Joy, Beichao Zhang, Liang Choo Hsia, Boon Meng Seah, Shyam Pal
  • STRESSED DIELECTRIC LAYER WITH STABLE STRESS
    Publication number: 20090250764
    Abstract: An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O3 TEOS oxide having a stress retaining dopant. The O3 TEOS oxide induces a stress in a channel region of the transistor.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Applicant: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Huang LIU, Jeff SHU, Luona GOH, Wei LU
  • VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE
    Publication number: 20090250818
    Abstract: An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
    Type: Application
    Filed: June 17, 2009
    Publication date: October 8, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Bei Chao Zhang, Chun Hui Low, Hong Lim Lee, Sang Yee Loong, Qiang Guo
  • INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS
    Publication number: 20090250762
    Abstract: An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Huang Liu, Wei Lu, Hai Cong, Alex K.H. See, Hui Peng Koh, Meisheng Zhou
  • Silicided polysilicon spacer for enhanced contact area
    Patent number: 7598572
    Abstract: An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: October 6, 2009
    Assignees: International Business Machines Corporation, Samsung Electronic Co., Ltd (Corporation), Chartered Semiconductor Manufacturing Ltd (Corporation)
    Inventors: Thomas W. Dyer, Sunfei Fang, Ja-Hum Ku, Yong Meng Lee
  • Gate stress engineering for MOSFET
    Patent number: 7595233
    Abstract: Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: September 29, 2009
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd
    Inventors: Zhijiong Luo, Yung Fu Chong, Huilong Zhu
  • Non-volatile memory cell with a hybrid access transistor
    Patent number: 7595237
    Abstract: A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: September 29, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Xiaoyu Chen, Donghua Liu, Sung Mun Jung, Swee Tuck Woo, Rachel Low, Louis Lim, Siow Lee Chwa
  • HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER
    Publication number: 20090236663
    Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
  • Modulation of stress in stress film through ion implantation and its application in stress memorization technique
    Patent number: 7592270
    Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 22, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Lee Wee Teo, Elgin Quek
  • INTERCONNECTIONS FOR INTEGRATED CIRCUITS
    Publication number: 20090233441
    Abstract: The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lup San Leong, Yong Kong Siew, Liang Choo Hsia
  • AVOIDING PLASMA CHARGING IN INTEGRATED CIRCUITS
    Publication number: 20090224326
    Abstract: A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit control terminal. The protection circuit having a protection control terminal is coupled to the primary circuit. The protection circuit includes a protection gate oxide of a second thickness T2 which is less than T1. The protection gate oxide reduces plasma induced damage in the primary circuit.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 10, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Chung Foong TAN, Jae Gon LEE, Lee Wee TEO, Elgin QUEK, Chunshan YIN
  • Process integration scheme of SONOS technology
    Patent number: 7585746
    Abstract: In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 8, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Sung Mun Jung, Yoke Leng Louis Lim, Sripad Nagarad, Dong Kyun Sohn, Dong Hua Liu, Xiao Yu Chen, Rachel Low
  • Combined copper plating method to improve gap fill
    Patent number: 7585768
    Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 8, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Xiaomei Bu, Alex See, Fan Zhang, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS
    Publication number: 20090218636
    Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
  • INTEGRATED CIRCUIT SYSTEM EMPLOYING RESISTANCE ALTERING TECHNIQUES
    Publication number: 20090221117
    Abstract: An integrated circuit system that includes: providing a substrate including a first region and a second region; forming a first device over the first region and a resistance device over the second region; forming a first dielectric layer and a second dielectric layer over the substrate; removing a portion of the second dielectric layer; and annealing the integrated circuit system to remove dopant from the resistance device.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Shyue Seng Tan, Lee Wee Teo, Chung Foong Tan, Jae Gon Lee, Elgin Kiok Boone Quek
  • METHODS FOR ENHANCING PHOTOLITHOGRAPHY PATTERNING
    Publication number: 20090214984
    Abstract: A method for fabricating a a semiconductor device that includes: providing a substrate prepared with a photoresist layer; providing a photomask comprising a first and a second pattern having a respective first and second pitch range; providing a composite aperture comprising a first and a second off-axis illumination aperture pattern, the first off-axis aperture pattern having a configuration that improves the process window of the first pitch range and the second off-axis aperture pattern having a configuration that improves the process window for a second pitch range; exposing the photoresist layer on the substrate with radiation from an exposure source through the composite aperture and the photomask; and developing the photoresist layer to pattern the photoresist layer.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 27, 2009
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Moh Lung LING, Gek Soon CHUA, Qunying LIN, Cho Jui TAY, Chenggen QUAN
  • NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
    Publication number: 20090206408
    Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
    Type: Application
    Filed: February 14, 2008
    Publication date: August 20, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
  • Method to form selective strained Si using lateral epitaxy
    Patent number: 7572712
    Abstract: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: August 11, 2009
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson R. Holt
  • Method to fabricate horizontal air columns underneath metal inductor
    Patent number: 7573081
    Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: August 11, 2009
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore
    Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
  • Semiconductor device layout and channeling implant process
    Patent number: 7573099
    Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: August 11, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yisuo Li, Xiaohong Jiang, Francis Benistant