Abstract: An improved shield for preventing the contamination of a wafer back from resist is combined with process steps that further prevent this contamination. The shield is located where vortex like air currents could otherwise deposit the resist vapor on the wafer back. The shield has the general shape of a cylinder that is open at the top and closed at the bottom. The bottom provides an attachment to a conventional part of the wafer coater and also forms part of the shield. The sides are arranged to extend close to the wafer back at a radius just less than the radius of the wafer. In the improved process, the spindle of the wafer chuck is not rotated at more than 1200 revolutions per minute in any of the wafer spinning operations, and the conventional step of washing the wafer back with a solvent is performed only at the end of the other operations.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A three-dimensional polysilicon capacitor for use within integrated circuits and a method by which the three-dimensional polysilicon capacitor is formed. Formed upon a semiconductor substrate is a first polysilicon layer which has a series of apertures formed at least partially through the first polysilicon layer. A conformal insulator layer is then formed upon the first polysilicon layer and into the apertures within the first polysilicon layer. The conformal insulator layer has a series of apertures corresponding to the series of apertures within the first polysilicon layer. A second polysilicon layer is then formed upon the surface of the conformal insulator layer and filling the apertures within the conformal insulator layer. Optionally, the first polysilicon layer may be formed from a multi-coating stack comprising two polysilicon coatings separated by an metal silicide etch stop layer.

Abstract: A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction.

Abstract: This computer system, as well as its method of operation, corrects the position data used to define the location of alignment marks on a workpiece. The first step is to scan marks along a first direction to determine the direction of wafer scaling along the first direction. Second, scan marks along a second direction to determine the direction of wafer scaling along the second direction. Next, scan a first set of alignment marks on a workpiece oriented in a first direction and a second set of alignment marks on the workpiece oriented in a second direction in an initial sequence to collect initial direction data on the location. Then, scan the first set of alignment marks and the second set of alignment marks in a reverse sequence to collect reverse direction data on the location. Finally, average the initial direction data and the reverse direction data. This enables correction of false alignment data attributable to falsely measured locations of alignment marks.

Abstract: A method for making low sheet resistance sub-quarter-micrometer gate electrode lengths on field effect transistors has been achieved. The method involves patterning gate electrodes on a silicon substrate from a conductively doped polysilicon layer having a silicon nitride layer on the surface. After forming the FET lightly doped drains (LDD), the sidewall spacers, and the heavily doped source/drain contact regions with titanium contacts, an insulating layer is chemically/mechanically polished back to the silicon nitride or silicon oxynitride on the gate electrode layer to form a planar self-aligning mask. A pre-amorphizing implantation is carried out, and a titanium silicide is selectively formed on the gate electrodes resulting in small grain sizes and much reduced sheet resistance. The self-aligned mask prevents ion implant damage to the shallow source/drain regions adjacent to the FET gate electrodes.

Abstract: An antireflection mask and method of using the antireflection mask to form contact holes for an integrated circuit wafer are described. The antireflection mask has a patterned opaque layer formed on a transparent mask substrate. The patterned opaque layer has first openings for exposing photoresist in regions where the photoresist is thicker and second openings for exposing photoresist in regions where the photoresist is thinner. A patterned layer of antireflection material having a light transmittance of less than 100% is formed over the second openings but not over the first openings. Light is passed through the mask to expose a layer of photoresist. The light exposing the thinner photoresist regions is attenuated by the antireflection material thereby compensating for variations in photoresist thickness. In addition the antireflection material reduces reflections from the patterned opaque layer of the mask.

Abstract: A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height.

Abstract: A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.

Abstract: The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and a first nitride layer 30 over a substrate. A first opening is formed in the pad oxide layer 20 and first nitride layer 30. The substrate is then etched through the first opening forming a first trench 40 in the substrate. A thin oxide film 50 is then grown over the substrate in the bottom and sidewalls of the first trench 40. Nitride spacers 60 are grown over the sidewalls of the first trench and over the thin oxide layer 40 on the sidewalls of the trench. A portion of the thin oxide film 50 on the bottom of the trench is etched. The substrate in the bottom of the first trench is etched forming a second trench 70. The etch exposes portions of the substrate on the bottom of the deeper second trench.

Abstract: A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode.

Abstract: A method for improving oxide quality by implanting both nitrogen and fluorine ions into the oxide layer through a polysilicon layer to prevent the penetration of impurities into the oxide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. Fluorine ions are implanted through the polysilicon layer wherein the fluorine ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. Thereafter, nitrogen ions are implanted through the polysilicon layer wherein the nitrogen ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. The substrate is annealed. The polysilicon and gate silicon oxide layers are patterned to form gate electrodes and interconnection lines.

Abstract: The present invention provides a structure and a method of manufacturing a resistor in a semiconductor device and especially for a resistor in an ink jet print head. The method begins by providing a substrate 10 having a field oxide region 20 surrounding an active area. The field oxide region 20 has an ink well region 52. Also a transistor is provided in the active area. The transistor comprises a source 12, drain 14 and gate electrode 16 18 19. A dielectric layer 24 is formed over the field oxide region 20 and the transistor 12 14 16 18. The dielectric layer 24 has contact openings over the source 12 and drain 14. A resistive layer 26 27 is formed over the dielectric layer 24 and contacting the source 12 and drain 14. The resistive layer 26 27 is preferably comprised of two layers of: a Titanium layer 26 under a titanium nitride 27 or a titanium layer 26 under a tungsten nitride layer 27. A first metal layer 28 is formed over the resistive layer.

Abstract: An improved antifuse design has been achieved by providing a structure comprising pair of alternating layers of silicon nitride and amorphous silicon sandwiched between two dual damascene connectors. Said structure provides the advantage, over the prior art, that all electrically active surfaces of the fuse structure are planar, so no potential failure spots resulting from surface unevenness can be formed. A process for manufacturing said fuse structure is also provided and involves fewer masking steps than related structures of the prior art.

Abstract: A process for forming metal composites, using a titanium underlay as part of the composite, with reduced risk of titanium adhesion loss or lifting, has been developed. Several solutions, resulting in protective layers being formed on the exposed titanium sidewall, have been shown. One solution features the addition of nitrogen, as part of reactive ion etching chemistry, during the patterning of the underlying titanium layer. The resulting titanium nitride formation, on the exposed titanium sidewall, protects against subsequent processing steps that may degrade the adhesion of titanium to an underlying material. A second solution describes the formation of a titanium oxide film on the exposed titanium sidewall. This formation occurs during a photoresist plasma strip, using an oxygen-stream ambient. The titanium oxide film again results in protection of the titanium interface, during subsequent processing steps.

Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

Abstract: An SRAM transistor cell on a doped semiconductor substrate comprises two access FET transistors and two storage FET transistors. A first load capacitor has a plate connected to a first node with the other plate connected to the power supply. A second load capacitor has a plate connected to the second node with the other plate connected to the power supply, a bit line and a bit line bar. The first storage transistor drain connects to the first node. The second storage transistor drain connects to the second node. The storage transistors have interconnected sources. The first node connects via a first interconnection line to the second transistor gate. The second node connects via a second interconnection line to the first transistor gate. First and second access transistor gates connect to a wordline. The first access transistor drain connects to the first node. The second access transistor drain connects to the second node. The first access transistor source connects to the bit line.