Abstract: A multi-level patterning process for use in the semiconductor fabrication technology that will consistently produce a very fine and well defined pattern, and which can be re-worked, especially at the early stages of the process is accomplished. In the process, a thick resist, such as a Novolak resin with suitable additives is spun on a wafer. This material is heavily dyed to the exposing wave length of the radiant energy source of the stepper. The planerizing layer is exposed to a silicon containing atmosphere, such as hexamethyldisilazane (HMDS) for a period of time and a temperature sufficient for the silicon to penetrate a short distance, for example about 0.25 micrometers into the resist. The resist is crosslinked during this bake or during a subsequent bake. These wafers are now ready for standard resist processing. The resist is spun, exposed, and developed. The wafers are then inspected for error. Rework can be accomplished at the stage by stripping the top resist and recoating.

Abstract: A structure formed by the method of forming a highly conductive electrical contact to a semiconductor region of an integrated circuits device is described. An opening to the semiconductor region is provided through an insulating layer. A thin first layer of aluminium having a first grain size is sputter deposited over and in the opening covering the surface of the semiconductor region. A second layer of aluminium having a second and substantially different grain size from the thin first layer of aluminium is sputter deposited thereover. The resulting aluminum structure is subjected in its normal process of manufacture to temperature cycling of greater than about 300.degree. C. whereby any formed silicon nodules are preferentially formed at the boundary of the thin first layer of aluminium and the second layer of aluminium. The second layer of aluminium may in one alternative completely fill the opening. In another alternative, a third layer has substantially the same grain size as the first aluminum.

Abstract: A new method of metallization of an integrated circuit is described. Semiconductor device structures are fabricated in and on a semiconductor substrate. At least one contact opening to the semiconductor substrate and at least one lithography alignment cross mark opening structure are formed. A barrier layer is preferably sputtered within the contact openings and over the semiconductor device structures. A cold aluminum seed layer is sputtered over all surfaces of the contact openings. Next, a hot aluminum flow layer is provided to obtain the desired step coverage of the contact openings. A second cold aluminum layer is then sputtered onto the hot aluminum layer to define the edges of the wide lithography alignment marks while maintaining good contact opening coverage.

Abstract: A new method to produce a contact or via opening and filled metallurgy for integrated circuits. An insulating layer structure is formed over semiconductor device structures. A resist mask with substantially vertical sided openings is formed in the mask over the insulating layer and above the device elements to be electrically contacted. These device elements can be, for example source/drain regions in the semiconductor substrate, a metallurgy layer interconnecting other device element and the like. The exposed insulating layer is isotropically etched to a depth of between about 500 to 850 Angstroms to form a break in the vertical sided opening under construction. The exposed insulating layer is anisotropically etched to complete the construction of the substantially vertical sided openings through the insulating layer to a device element to be electrically contacted.

Abstract: A process and for fabricating field oxide isolation pattern with field implants associated therewith that can be used for increasingly smaller dimensional elements, for example in feature sizes of 0.8 micrometers or less, and simpler processing than the prior art is described. A semiconductor substrate is provided. A multilayer oxidation masking structure of a thin silicon oxide layer, a silicon nitride layer, and a polycrystalline silicon layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and the polycrystalline silicon layer from the areas designated to have field oxide isolation grown therein to form a narrow opening. The structure is exposed to an oxidizing environment such that the polysilicon oxide layer forms an "overhang" over part of the field isolation region. Ion implanting in a vertical direction is accomplished to form the field implant in the silicon surface of the dimension of the narrow opening less the overhang.

Abstract: Ion Implantation is used to cure spin-on-glass layers. Ions, such as Argon or Arsenic are implanted into the spin-on-glass layer of an article. The action of the ion moving through the spin-on-glass layer causes internal heating. This heating cures the spin-on-glass layer of the article.

Abstract: A method for fabricating an integrated circuit having a double polysilicon capacitors and metal oxide silicon field effect devices which are compatible to one micrometer or less processing is described. First, a pattern of recessed oxide isolation is formed on the surface of a silicon substrate. The pattern separates surface regions of silicon from other such regions. A gate dielectric layer is formed on the surface of surface regions of the silicon with a suitable dopant concentration. A first polysilicon layer is formed over the gate dielectric layer and over the field oxide having a suitable doping concentration. An interpoly dielectric layer is formed over the surface of the first polysilicon layer. A second poly silicon layer is formed over the interpoly dielectric layer having a suitable doping concentration. The second polysilicon layer is patterned using a first resist masking and suitable etching to leave only the top plate of the capacitor in the second polysilicon layer.