Abstract: The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.

Abstract: A microloading quantification apparatus is comprising a supporting substrate, a first bonding pad deposited upon the supporting substrate, a second bonding pad deposited upon the supporting substrate, and an etched conductive pattern deposited upon the supporting substrate and operably connected to the first bonding pad and the second bonding pad. Methods for the formation and application of the microloading quantification apparatus to quantify the variation of the microloading effect as a result of modifications of the set of parameters of integrated circuit processing particularly those of the plasma dry etch are described.

Abstract: A method for forming a double layer planar polysilicon capacitor for use within integrated circuits is presented. Formed within a semiconductor substrate is a deep trench which is filled with a dielectric material. Formed within the dielectric material within the deep trench is a shallow trench which has a first polysilicon capacitor plate formed therein. The upper surface of the first polysilicon capacitor plate is substantially planar with the semiconductor substrate. Formed upon the first polysilicon capacitor plate is a polysilicon capacitor dielectric layer. Formed upon the polysilicon capacitor dielectric layer is a second polysilicon capacitor plate.

Abstract: A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening.

Abstract: A method for fabricating an improved connection between active device regions in silicon, to an overlying metallization level, has been developed. The method produces contacts with superior and improved barrier integrity, which permits silicon device exposure to extended thermal process times and/or higher temperature processes without metal penetration into the silicon contact junction regions. The critical element is the addition of a conformal CVD tungsten layer in the multilayer barrier structure.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: A method for forming self-aligned twin wells without height difference using only one masking step is described. A layer of silicon oxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. A layer of photoresist is coated over the silicon nitride layer. The photoresist layer is exposed to actinic light and developed to form a photoresist mask having an opening to the silicon nitride layer where an N-well is to be formed. The silicon nitride layer which is exposed is etched away to expose the underlying silicon oxide layer. First ions are implanted into the semiconductor substrate through the silicon oxide layer within the opening. A dielectric film is deposited over the substrate. The dielectric film is planarized to the height of the silicon nitride layer. The silicon nitride layer is removed. Second ions are implanted into the semiconductor substrate where it is not covered by the dielectric film. The dielectric film is removed.

Abstract: An analog capacitor is formed as part of an integrated circuit, using normal manufacturing methods, and then the upper electrode of this capacitor is used as part of the end point detection scheme during chem.-mech. polishing (CMP). Said upper electrode is formed from polysilicon and as soon as its upper surface is exposed as a result of the CMP, the presence of silicon particles in the removed material is readily detected by one of several possible methods.

Abstract: A chemical mechanical planarization polishing machine that includes a means for the detection of planarization end point is described. The chemical mechanical planarization polishing machine includes a workpiece carrier to hold and rotate a semiconductor wafer workpiece. The semiconductor wafer workpiece is placed in contact with a rotating polishing pad onto which an abrasive slurry is dispensed. A light emitting means directs a beam of light onto the workpiece carrier. The beam of light is reflected to a positional sensing means that detects variation in the position of the reflected beam of light as the workpiece vibrates due to irregularities in the surface of the workpiece. The positional information of the variation of the reflected beam of light is transferred to a calculating means that will determine the planarization end point from changes in magnitude and frequency of the positional information and a predetermined relationship between the vibration of the workpiece and the planarization end point.

Abstract: An improved antifuse design has been achieved by using a structure including a region of heavily doped N type silicon coated with a layer of ONO (oxide-nitride-oxide). Top contact to the ONO is made through a layer of tungsten silicide sandwiched between two layers of N type polysilicon. A cost effective method for manufacturing said antifuse structure is described.

Abstract: A method for forming a low contact leakage and low contact resistance integrated circuit device electrode within an integrated circuit, and the low contact leakage and low contact resistance integrated circuit device electrode formed through the method. There is first formed within a semiconductor substrate an integrated circuit device electrode. The integrated circuit device electrode has a width upon the semiconductor substrate of less than the width of a conductor element desired to be formed upon the integrated circuit device electrode plus two times the registration tolerance of a fabrication tool employed in defining the location of the conductor element desired to be formed upon the integrated circuit device electrode. Formed then upon the semiconductor substrate including the integrated circuit device electrode is a blanket metal silicide forming metal layer.

Abstract: A process for creating narrow, metal via structures, used to connect metallization levels, has been developed. The process features initially forming a narrow, metal via structure, and then an underlying interconnect metallization structure, from a single, composite metallization layer. The composite metallization layer is composed of conductive layers, with a specific layer used as an etch stop, allowing creation of a narrow metal via structure, from the top layer of the composite metallization layer, without disturbing the bottom layers. The bottom layers of the composite metallization layer are then patterned to create the underlying interconnect metallization structure.

Abstract: The present provides a method of manufacturing a planar field isolation region using a polysilicon layer as a polishing stop. The method begins by sequentially forming an insulating layer 12, a polysilicon layer 14 and a nitride layer 16 over a primary surface of a substrate 10. The polysilicon layer 14 and the nitride layer 16 are patterned to form a first opening exposing insulating layer 12. A field isolation region is grown to a first thickness within the first opening. The nitride layer is removed. The field isolation region is polished so that the top surface of the field isolation region is coplanar with the top surface of the polysilicon layer. Next the polysilicon layer is removed by either of two embodiments. First, the polysilicon is removed by a second (CMP) polishing step which uses a different slurry than the field oxide CMP. The second CMP step the exposed surface of the field isolation region is coplanar with an exposed surface of the polysilicon layer.

Abstract: A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction.

Abstract: A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow metal via stud structures, and filling the spaces between the metal via stud structures with a planarizing layer of a composite dielectric, which includes a spin on glass layer. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.

Abstract: A flash memory EEPROM transistor is formed on a surface of a semiconductor substrate. In portions of the substrate, at the surface thereof, a doped source region and a doped drain region are formed with a channel region therebetween. A tunnel silicon oxide dielectric layer is formed over the semiconductor substrate aside from the source region. Above the source region is formed a gate oxide layer which is thicker than the tunnel oxide layer. Above a portion of the tunnel oxide dielectric layer, over the channel region and above a portion of the gate oxide layer is formed a stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer. The source region is located on one side of the stacked gate structure with one edge of the source region overlapping the gate structure. The drain region which is located on the other side of the stacked gate structure with one edge thereof overlapping the gate structure.

Abstract: A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.

Abstract: A method for forming a residue free patterned conductor layer upon a high step height integrated circuit substrate. First, there is provided a semiconductor substrate having formed thereon a high step height patterned integrated circuit layer. Formed upon the high step height patterned integrated circuit layer is a blanket conductor layer, and formed upon the blanket conductor layer is a patterned photoresist layer. The portions of the blanket conductor layer exposed through the patterned photoresist layer are etched through an anisotropic etch process to leave remaining a patterned conductor layer upon the surface of the high step height patterned integrated circuit layer and conductor layer residues at a lower step level of the high step height patterned integrated circuit layer. The patterned photoresist layer is then reflowed to cover exposed edges of the patterned conductor layer.