Abstract: A process has been developed in which planar, multilevel metallizations, are used to fabricate semiconductor devices. The process features initially forming tall, narrow photoresist plugs, and filling the spaces between photoresist plugs with a planarizing layer of a composite dielectric, which includes a spin on glass layer. Removal of the photoresist plug results in the creation of a narrow via hole. The composite dielectric was deposited by initially using a non-porous, silicon oxide layer, followed by the planarizing spin on glass layer. Therefore metal via fills will interface the non-porous, silicon oxide layer.

Abstract: A method for dry etching a composite metal film, consisting of an aluminum overlay film, a titanium--tungsten film, and a titanium underlay film, is described. The process uses an organic photoresist as a mask and features improved etch selectivity and non-tapered sidewalls. The addition of CF.sub.4, to the etching chemistry used to pattern titanium--tungsten films, increases the selectivity between the photoresist and titanium--tungsten, allowing for thinner resists to be used, and thus finer resolution to be achieved. The introduction of N2 to the etching chemistry results in a N.sub.2 containing polymer to be formed during the etching procedure, on the sidewalls of the etched structure. The polymer prevents the isotropic component of the reactive ion etching process to attack the metal structure, thus allowing for non-tapered structures to be obtained.

Abstract: A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.

Abstract: A method for improving oxide quality by implanting both nitrogen and fluorine ions into the oxide layer through a polysilicon layer to prevent the penetration of impurities into the oxide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. Fluorine ions are implanted through the polysilicon layer wherein the fluorine ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. Thereafter, nitrogen ions are implanted through the polysilicon layer wherein the nitrogen ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. The substrate is annealed. The polysilicon and gate silicon oxide layers are patterned to form gate electrodes and interconnection lines.

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with limited susceptibility to Hot Carrier Effects (HCEs), and a method by which that MOSFET is formed. There is first provided a semiconductor substrate which has a first portion, a second portion adjoining a side of the first portion and a third portion adjoining an opposite side of the first portion. Formed upon the first portion of the semiconductor substrate is a gate oxide layer which has a gate electrode formed and aligned thereupon. The gate electrode has a first sidewall adjoining the second portion of the semiconductor substrate and a second sidewall adjoining the third portion of the semiconductor substrate. Formed upon the first sidewall of the gate electrode and upon the surface of the second portion of the semiconductor substrate adjoining the first sidewall is a conformal oxide layer. The conformal oxide layer has a dose of fluorine atoms incorporated therein.

Abstract: A method for forming an LDD structure using a self-aligned halo process is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A gate electrode is formed overlying the gate silicon oxide layer. A silicon oxide layer is grown on the sidewalls of the gate electrode and silicon nitride spacers are formed on the sidewalls of the silicon oxide layer. First ions are implanted into the semiconductor substrate and the substrate is annealed whereby heavily doped source and drain regions are formed within the semiconductor substrate not covered by the gate electrode and the silicon oxide and silicon nitride spacers. An oxide layer is grown over the heavily doped source and drain regions. Thereafter, the silicon nitride spacers are removed. Second ions are implanted to form lightly doped regions in the semiconductor substrate not covered by the oxide layer. Third ions are implanted to form a halo having opposite dosage and a deeper junction than the lightly doped regions.

Abstract: A method for dry etching metal films, specifically aluminum, is described. This process uses photoresist as a mask with a gas mixture of BCl3, Cl2 and N2 used for the RIE. The addition of specific amounts of N2 to the etching chemistry results in non-tapered or non-undercut aluminum shapes. These desired shapes are attributed to the creation of polymer on the sidewall of the aluminum during the etching procedure, thus protecting against the isotropic components of RIE process, which cause the tapering. This RIE process can also be conducted at high enough temperatures, needed to avoid deleterious microloading effects.

Abstract: This invention provides a structure and a method of forming a capacitor with a high unit capacitance for use in analog circuits and a bond pad which will eliminate bond pad peeling during subsequent processing. The bottom capacitor plate is formed at the same time the bond pads are formed. The bottom capacitor plate and the bond pads are formed using a conducting material such as doped polysilicon, which will eliminate bond pad peeling during subsequent processing. The top capacitor plate is formed when the top electrode pattern is formed. This integrated process provides a bond pad which will eliminate bond pad peeling during subsequent process steps and a capacitor with high unit capacitance for use in analog circuits.

Abstract: A Reactive Ion Etch (RIE) plasma method for removing from semiconductor substrates oxidized organic residues such as oxidized photoresist residues, and the Reactive Ion Etch (RIE) plasma which is employed within the Reactive Ion Etch (RIE) plasma method. A semiconductor substrate upon whose surface resides an oxidized organic residue such as an oxidized photoresist residue is provided into a Reactive Ion Etch (RIE) plasma chamber. Also provided into the chamber is a concentration of oxygen and a concentration of moisture. Finally, a radio frequency excitation of sufficient magnitude is provided to the concentration of oxygen and the concentration of moisture to form a plasma. The oxidized organic residue which resides upon the semiconductor substrate is then removed through etching in the Reactive Ion Etch (RIE) plasma.

Abstract: There is described a spin coating apparatus for applying a liquid material to a semiconductor wafer, or the like, that has a spin head for supporting a wafer on the top surface, a motor to rotate the spin head, and a nozzle located over the spin head for dispensing liquid on the wafer mounted on the spin head. A liquid well is provided having a bottom outlet opening, a bottom inlet opening, a top vent opening, and a heat exchange jacket on at least the well side walls. A shut-off valve is located between the nozzle and well, with the inlet of the valve communicating with the bottom outlet of the well, and the inlet of the valve communicating with the nozzle. A liquid supply source provides liquid to the well through the inlet opening of the well. A multi-stage vent and purge system is provided to vent and selectively introduce either gas or liquid cleaning medium into the well through the top vent opening. The distance between the nozzle and the spin head is controlled with a nozzle support.

Abstract: A new method of forming a back diffused resistive load element is achieved. A pattern of gate electrodes and interconnection lines is formed overlying a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate. An interpoly oxide layer is deposited overlying the top surfaces of the semiconductor substrate and etched away where it is not covered by a mask to provide an opening to a drain region within the semiconductor substrate and exposing a portion of a gate electrode wherein a spacer comprising interpoly oxide is left on the sidewall of the exposed gate electrode within the opening. In order to remove the interpoly oxide spacer, the interpoly oxide layer is overetched whereby the top portion of the drain region in the semiconductor substrate is etched away along with a portion of the dopant. First ions are implanted into the drain region and the exposed portion of the gate electrode.

Abstract: This invention provides a method for converting residual chlorine, remaining after using a chlorine specie etchant to etch metal electrodes in an integrated circuit device, to a stable polymer thereby eliminating any possibility for residual chlorine to cause corrosion of the metal electrodes. In conventional processing residual chlorine ions can combine with moisture and cause immediate corrosion of metal electrodes or can cause corrosion over time resulting in a degradation of device reliability. This invention provides a method of baking the integrated circuit device in an atmosphere of CF.sub.4, O.sub.2, or CF.sub.4 and O.sub.2 at elevated temperature, thereby converting any residual chlorine to a stable polymer. Since all the available chlorine is stabilized free chlorine is no longer available as a corrosion hazard.

Abstract: This invention provides an improved process latitude mask for forming contact or via hole openings in a photoresist masking layer in the fabrication of semiconductor integrated circuits. The invention also provides a method of forming contact or via hole openings in a photoresist masking layer using an improved process latitude mask. The improved process latitude mask, called a dot mask, uses an opaque blocking area formed in the center of the primary opening in a projection mask for forming contact or via hole openings in a photoresist layer. The opaque blocking area is equal to or less than the area of the primary opening divided by nine. The opaque blocking area is small enough so that it will not form an image in the photoresist layer. The opaque blocking area modifies the light intensity profile at the photoresist layer in a manner which improves process latitude.

Abstract: A station for coating a semiconductor wafer with a photoresist is provided with a detector for bubbles that may occur in the resist that is supplied to the wafer. The resist is carried to the coating apparatus by a plastic tube. A commercially available capacitance detector is positioned to detect the dielectric constant of the combination of the tube, the resist, and any bubbles in the resist. The dielectric constant of the bubbles is lower than the dielectric constant of the resist, but the difference is not sufficient for detecting the bubbles with the capacitance detector alone. A metal backing plate is located on the side of the tube opposite the detector and enhances the operation of the detector sufficiently to detect bubbles of various sizes.

Abstract: This invention provides a method of forming contact holes and via holes in interlevel dielectric which insure good metal stepcoverage. The contact or via holes have tapered sides and smoothed edges. The method uses isotropic etching, anisotropic etching, and argon sputter etching in vacuum and does not require high temperature contact reflow. The final argon sputter etch is a timed etch that smoothes all sharp edges, exposes the regions where electrical contact will be made, and planarizes the interlevel dielectric.

Abstract: A method for dispensing fluids on a semiconductor wafer wherein a wafer is mounted on a rotatable chunk, a fluid to be dispensed is introduced into a well through an inlet located adjacent the bottom of the well, rotating the chunk and moving a soft inpact dispensing nozzle, that draws bubble-free fluid from the bottom of the well, over the wafer, and dispensing the fluid at a low pressure and a short distance to the wafer surface.

Abstract: A method, and resultant structure, for manufacturing large highly reflective metal reflector plates on an integrated circuit chip, for applications in game chips or similar virtual image projection systems, is described. A metal interconnection layer is formed above a semiconductor substrate, an intermetal dielectric layer is formed on the metal interconnection layer, and an opening is made through the intermetal dielectric layer to expose a portion of the metal interconnection layer. A first metal layer is formed on the intermetal dielectric layer and connecting to the metal interconnection layer through the opening. A second metal layer is formed on the first metal layer. A third metal layer is formed on the second metal layer. A highly reflective metal layer is formed on the third metal layer. The the first, second, third and highly reflective metal layers are patterned to form the highly reflective metal reflector plate.

Abstract: An improved electrically programmable and erasable memory device having a plurality of addressable single transistor cells, each transistor having spaced source and drain regions, a floating gate and a control gate. The improvement is a new tunneling insulator layer structure between the floating gate and the control gate. The improved tunneling layer is a dual layer formed of a outer silicon oxide layer and an inner silicon oxynitride layer.

Abstract: A new method of forming a polysilicon resistor is achieved. Polysilicon gate structures and source/drain regions are formed in and on a semiconductor substrate. A passivation layer is formed overlying the gate structures. A contact window is opened to the drain portion of the source/drain region. A resistor is formed within the contact window as follows. A nitride layer is deposited over the passivation layer and within the contact window. The nitride layer is etched back to form nitride sidewalls within the contact window. A layer of polysilicon is deposited over the passivation layer and within the contact window. The polysilicon layer is etched back to leave the polysilicon only within the contact opening completing formation of the resistor. A second contact window is opened to the source portion of the source/drain region. A barrier metal layer is deposited over the passivation layer, over the resistor, and within the second contact window.

Abstract: A new method of forming contact or via openings is achieved. A photoresist layer is formed and patterned top of layers of insulating materials overlying a semiconductor substrate. An isotropic etch is performed etching both vertically and horizontally a portion of the insulating layers. The photoresist is pulled back via a pure isotropic etch. Since the resist is being etched threedimensionally, an overhang resist profile is formed at the top of the opening. The opening is completed by anisotropically etching the remainder of the contact or via opening. The overhang part of the resist is recessed back gradually during etching. The oxide is exposed gradually through and together with the resist recessing back. The step formed after the first isotropic etch will be exposed to the anisotropic etch and will be etched into a slope.