Patents Assigned to ChipPAC, Inc.
  • Patent number: 8970049
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 3, 2015
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8623704
    Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: January 7, 2014
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon
  • Patent number: 8552551
    Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: October 8, 2013
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 8169064
    Abstract: A package on package system is provided including providing a first substrate having a first integrated circuit thereon and a second substrate having a second integrated circuit thereon, the second substrate having a recess provided therein. The first and second substrates are mounted having the first integrated circuit at least partially nested in the recess.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: May 1, 2012
    Assignees: Stats Chippac Ltd., Stats Chippac, Inc.
    Inventor: Hyun Uk Kim
  • Patent number: 8143100
    Abstract: A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 27, 2012
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8129231
    Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 6, 2012
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Oh Sug Kim, Byung Tai Do
  • Patent number: 8129263
    Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 6, 2012
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Patent number: 8115301
    Abstract: Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected regions not occupied by the flip-chip. A heat-spreader is applied to contact the applied adhesive without contacting the back-side of the flip-chip, leaving a gap between the heat-spreader and the back-side of the flip-chip. The heat-spreader defines at least one through-hole that, when the heat-spreader is placed, is within a perimeter of the flip-chip. The adhesive is cured, and a thermal-insulating material (TIM) is applied through the at least one through-hole so as to fill the gap with the TIM. The methods substantially reduce the probability of die damage that otherwise occurs during attachment of heat-spreaders.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 14, 2012
    Assignee: STATS ChipPAC, Inc.
    Inventors: KyungOe Kim, YoungJoon Kim, HyunSoo Shin
  • Patent number: 8106496
    Abstract: A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: January 31, 2012
    Assignee: Stats Chippac, Inc.
    Inventors: Kambhampati Ramakrishna, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8037918
    Abstract: Pick-up heads and systems are especially useful for picking up, transporting, and placing semiconductor dies at bond sites on packaging substrates. Alternatively, the heads and systems are useful for performing these tasks with any of various other planar objects. An exemplary head includes a shank and a body. The body includes a compliant end portion contactable by the shank, and the end portion includes a face. The shank is movable relative to the end portion such that, whenever the shank is retracted, the face has a substantially planar contour, and whenever the shank is extended, the shank contacts and urges the end portion to provide the face with a convex contour. The end portion desirably defines at least one vacuum orifice connected to an evacuation device (e.g., a vacuum pump) that evacuates the vacuum orifice sufficiently to cause the planar object to adhere to the face.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Ya Ping Wang, Jian Ming Yang, Guo Qiang Shen, Chee Keong Chin
  • Patent number: 8035205
    Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 11, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Seong Won Park, Cheng Yu Hsia, Yong Suk Kim
  • Patent number: 8030134
    Abstract: Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 8030756
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 8021931
    Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 20, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Dario S. Filoteo, Jr., Emmanuel A. Espiritu
  • Patent number: 7994626
    Abstract: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac, Inc.
    Inventor: Rajendra D. Pendse
  • Patent number: 7986047
    Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: July 26, 2011
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Patent number: 7952211
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: May 31, 2011
    Assignee: Stats Chippac, Inc.
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Patent number: 7935572
    Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 3, 2011
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7880313
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 1, 2011
    Assignee: Chippac, Inc.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Patent number: 7829382
    Abstract: A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: November 9, 2010
    Assignee: Chippac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim