Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along an edge of the package, and in some embodiments in a row along each of the four edges of the package. The leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other; in a plan view, the leads of the first leadframe appear to be interdigitated with the leads of the second leadframe. The input/output contact portions of the first leadframe are exposed in a row of first contacts near or, usually, at the edge of the package, and the input/output contact portions of the second leadframe are exposed in a row of second contacts inboard from the row of first contacts.

Abstract: A substantially lead-free solder composition having the composition (weight %): Sn, 76.0-83.9%; Ag, 8.0-12.0%; Sb, 8.0-10%; Cu, 0.1-2.0%. In some embodiments the solder composition contains 12 wt % Ag, 8 wt % Sb, 0.1 wt % Cu, the remainder being Sn. The solder can be formed into a wire, a ribbon or sheet, a solder paste or preform, or a powder, for example. Fillers, such as Si or Ag spherical fillers, with a particle size maximum at 35 ?m, can be added to any of the various solder forms during alloy fabrication. Also, a semiconductor package having a die attached to a support using the substantially lead-free solder composition.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: Apparatus and center pad die and substrate assemblies configured to provide for molding, in a single molding step, both an attached center pad die and other features on a die attach side of the substrate, and wire bonds an associated bond pads and other features on the opposite side of the substrate. Also, methods for sealing a center pad die and substrate assembly, including such a molding step.

Abstract: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-down flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: A semiconductor multi-package module has a second package inverted and stacked over a first package, each of the packages having a die attached to a substrate, in which the second package substrate and the first package substrate are interconnected by wire bonding, and in which the first package includes a ball grid array package. Also, a method for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.

Abstract: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).

Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-down configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages includes a stacked die package, or includes an additional stacked package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, in which one or both of the upper and lower packages is a stacked die package or in which one of the packages includes an additional stacked package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.