Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.

Abstract: A COF package structure includes a flexible substrate and a chip. A chip mounting area is defined on an upper surface of a flexible base of the flexible substrate. A circuit layer of the flexible substrate includes a plurality of first upper leads, second upper leads, first conductive vias and lower leads. The second upper leads are disposed in the chip mounting area and divided into groups, and each second upper lead has a second inner end and an upper pad opposite to each other. The upper pads of each group are arranged layer by layer into at least two rows. There are two upper pads symmetrically arranged on both sides of a reference line of each group on at least one row furthest from the second inner ends. The first conductive vias connect the upper pads and the lower leads. The chip is mounted in the chip mounting area.

Abstract: Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. The second chip is flipped on the chip bonding zone. The first conductive bumps are disposed on the first outer pads. The second conductive bumps are disposed between the first inner pads of the first chip and a plurality of second pads of the second chip. The underfill is disposed on the first active surface and covers the second conductive bumps, at least a part of each second chip lateral and at least a part of each first conductive bump. Multiple semiconductor package manufacturing methods are further provided.

Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the pad. The re-distribution layer structure includes a first and a second patterned insulating layers and a re-distribution layer. The first patterned insulating layer is disposed on the protective layer and includes at least one trench and a second opening corresponding to the first opening. The re-distribution layer is disposed on the first patterned insulating layer and includes a pad portion and a wire portion. The pad portion is located on the first patterned insulating layer. The wire portion includes a body and at least one root protruding from the body and extending into the trench. The body extends from the pad portion to the pad exposed by the first and the second openings. The second patterned insulating layer covers the wire portion and exposes a part of the pad portion.

Abstract: A fingerprint sensor chip package structure including a circuit carrier and a fingerprint sensor chip is provided. The fingerprint sensor chip is disposed on the circuit carrier. The fingerprint sensor chip includes a chip body and a plurality of sensing structures. The chip body has an active surface, a fingerprint sensing back surface, a plurality of bond pads disposed on the active surface and a plurality of through holes. The chip body is electrically connected to the circuit carrier with the active surface facing the circuit carrier. The sensing structures are disposed in the through holes respectively. Each of the sensing structures includes a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer. The first dielectric layer is exposed on the fingerprint sensing back surface. The second metal layer extends to the active surface to be electrically connected to the corresponding bond pad.

Abstract: Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

Abstract: A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (Ag1-xYx) layer, wherein the Y of the Ag1-xYx layer includes metals forming a complete solid solution with Ag at arbitrary weight percentage, and the X of the Ag1-xYx layer is in a range from about 0.02 to 0.15. The fabricating method thereof is also provided.

Abstract: A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the pad. The re-distribution layer structure includes a first and a second patterned insulating layers and a re-distribution layer. The first patterned insulating layer is disposed on the protective layer and includes at least one protrusion and a second opening corresponding to the first opening. The re-distribution layer is disposed on the first patterned insulating layer and includes a pad portion and a wire portion. The pad portion is located on the first patterned insulating layer. The wire portion includes a body and at least one trench caved in the body. The body extends from the pad portion to the pad exposed by the first and the second openings. The body covers the protrusion, and the at least one protrusion extends into the at least one trench. The second patterned insulating layer covers the wire portion and exposes a part of the pad portion.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A solder ball includes a silver ball structure and a shell structure. The shell structure wraps a surface of the silver ball structure, and a material of the shell structure at least includes tin. When the solder ball is bonded to other devices, the ball height of the solder ball remains constant to avoid collapse.

Abstract: A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

Abstract: A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.