Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Abstract: A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.

Abstract: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

Abstract: A laser mark is inscribed on an IC component, which character stroke consists of a plurality of laser paths inscribed by a laser beam. The width of the character stroke is greater than the widths of the laser paths. In addition, at least two of the laser paths, moving in opposite directions or in a same direction of the laser beam, are integrally connected as a laser-inscribing stroke to reduce end-to-end breaks between the laser paths.

Abstract: This invention provides a wafer testing system and testing method thereof. The wafer testing system comprises a wafer storage section, a prober, a tester, an RFID middleware unit, an EDA system and an MES system. The wafer storage section stores a multiplicity of carriers, each of which is provided with at least a RFID tag. The prober comprises a RFID reader to read a tag information. The tester sends a test signal to the prober for implementing the wafer test so as to generate a test result and calls an interface program to convert the test result into a file conformed with a specific data format. The RFID middleware unit receives the tag information and calls related applications to process the tag information so as to generate a wafer information. The EDA system receives the file of the specific data format converted from the interface program and calculates thereof to generate a wafer yield information after wafer test.

Abstract: The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the first inner leads is greater than that of the second inner leads; and a plurality of semiconductor chip devices. The active surface of each chip faces upward and chips are misaligned to form offset stacked structure, wherein the semiconductor chip device stacked uppermost is fixedly connected under said first inner leads, and the plurality of semiconductor chip devices are electrically connected to the first inner leads and the second inner leads on the same side edge.

Abstract: The present invention provides a flexible substrate for a package of a die which has an active surface and a plurality of first bond pads arranged in a form of a row and formed on the active surface. The flexible substrate includes a flexible insulating film and a plurality of first leads formed on the flexible insulating film. Each of the first leads corresponds to one of the first bond pads and has a respective first body portion, a respective first bond portion and a respective first extension portion. For each of the first leads, the width of the first bond portion is larger than those of the first body portion and the first extension portion.

Abstract: A multi-chip image sensor module includes a flexible module board, an image sensor chip, a transparent cover, and at least an IC chip. The flexible module board has a first die-attached portion, a second die-attached portion, at least one bent portion, and at least one bonding portion where the bent portion connects the first die-attached portion and the bonding portion. The image sensor chip is attached to the first die-attached portion and the IC chip is disposed on the second die-attached portion. Inner leads on the bonding portion are electrically connected to the bonding pads of the image sensor chip when the bonding portion is bonded on the image sensor chip. The transparent cover is disposed above the sensing area of the image sensor chip, preferably adhered to the bonding portion.

Abstract: A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of the probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.

Abstract: A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.

Abstract: A modularized probe card with coaxial transmitter is disclosed. At least a coaxial transmitter is modularized and installed between a first printed circuit board and a second printed circuit board. The coaxial transmitter has a first connector and a second connector correspondingly connecting two ends of each coaxial cable of the coaxial transmitter for electrically connecting corresponding in location to first printed circuit board and second printed circuit board. A probe head is bonded on second printed circuit board. The second connector of the coaxial transmitter is connected with the second printed circuit board in a plug-in and pull-away type.

Abstract: A modularized probe card comprising an interface board, a probe head and at least a compressible electrical connection device is disclosed. The compressible electrical connection device comprises an insulation layer with a plurality of circuits on one of its surface. Two ends of each circuit connect respectively to the first contacting pad and the second contacting pad which combine with elastic contact members. Each elastic contact member has a supporter combining with a conductive layer for electrical connections by pushing and compressing. While a probe head is modularized installed on an interface board, the elastic contact members of the compressible electrical connection device is elastically contacted and compressed the probe head and the interface board to acquire modularized electrical connection of the probe card.

Abstract: A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

Abstract: A SOC (Substrate-On-Chip) packaging process is disclosed. A layer of two-stage thermosetting mixture with solvent is coating on an upside of a substrate. Thereafter, the substrate is heated for removing solvent so that the two-stage thermosetting mixture becomes a B-stage dry adhesive film without solvent. Thus, the bonding pads of the chip are not covered by the dry adhesive film and a better operating flexibility is obtained in the SOC packaging process.

Abstract: A flip chip type semiconductor device for reducing signal skew includes: a chip with bonding pads, and a plurality of bumping pads on the chip. Between each bonding pad and corresponding bumping pads is connected with a metal redistribution trace covered by a passivation layer. Each metal trace has an equal trace length for reducing signal skew.

Abstract: A manufacturing process of semiconductor devices comprises providing at least a wafer, bumping the wafer, testing the wafer, laser repairing, and dicing.