Abstract: A chip package structure including a chip, a circuit layer, a passive element material and a substrate is provided. The circuit layer is disposed on a surface of the chip, wherein the circuit layer includes a plurality of bumps and a plurality of passive element electrodes. The bumps and the passive element electrodes have the same material, and the passive element electrodes are electrically connected with part of the bumps. The passive element material is disposed between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element located on the surface of the chip. The chip is disposed on the substrate and faces the substrate by the surface, so that the chip and the passive element are electrically connected to the substrate through the bumps. A method of manufacturing the chip package structure aforementioned is also provided.

Abstract: A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads.

Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.

Abstract: A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

Abstract: A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.

Abstract: A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions are exposed on the package bottom surface.

Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.

Abstract: A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

Abstract: A manufacturing method for a micro bump structure includes the following steps as follows. A substrate is provided and a under bump metallurgy (UBM) is formed on the substrate for accommodating a solder ball. A buffer layer is disposed on the substrate and then the solder ball is disposed on the UBM. Finally, the solder ball is grinded in order get the height reduced to a predetermined height.

Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

Abstract: A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.

Abstract: The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

Abstract: A semiconductor structure includes a device, a conductive pad over the device and a Ag1-xYx alloy pillar disposed on the conductive pad, wherein the Y of the Ag1-xYx alloy comprises metals forming complete solid solution with Ag at arbitrary weight percentage, and wherein the X of the Ag1-xYx alloy is in a range of from about 0.005 to about 0.25.

Abstract: A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.

Abstract: A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.

Abstract: The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.

Abstract: The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer on the substrate; forming an opening on the mask layer; depositing a conductive layer in the opening; forming a cap layer on the conductive layer, and removing the mask layer. The cap layer forming step allows the contacting area between the cap layer and the conductive layer to be substantially equal to the top surface area of the conductive layer by reflowing solder material prior to the removal of the mask layer.

Abstract: A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.

Abstract: A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires.