Patents Assigned to ChipPAC, Inc.
  • Patent number: 8970049
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 3, 2015
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8623704
    Abstract: An adhesive/spacer structure (52, 52A, 60) is used to adhere first and second die (14, 18) to one another at a chosen separation in a multiple-die semiconductor chip package (56). The first and second die define a die bonding region (38) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands (52, 52A) securing the first and second die to one another at a chosen separation (53). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: January 7, 2014
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon
  • Patent number: 8552551
    Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: October 8, 2013
    Assignee: CHIPPAC, Inc.
    Inventors: Sang Ho Lee, Jong Wook Ju, Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 8143100
    Abstract: A method for making a semiconductor multi-package module includes; providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 27, 2012
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8129263
    Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 6, 2012
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Patent number: 8030756
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 8030134
    Abstract: Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 4, 2011
    Assignee: Chippac, Inc.
    Inventors: Hyeog Chan Kwon, Marcos Karnezos
  • Patent number: 7986047
    Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: July 26, 2011
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Patent number: 7935572
    Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 3, 2011
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7880313
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: February 1, 2011
    Assignee: Chippac, Inc.
    Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
  • Patent number: 7829382
    Abstract: A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: November 9, 2010
    Assignee: Chippac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Patent number: 7749807
    Abstract: A method for making a semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: July 6, 2010
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7745322
    Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: June 29, 2010
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse
  • Patent number: 7732254
    Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: June 8, 2010
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20100083494
    Abstract: A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.
    Type: Application
    Filed: December 10, 2009
    Publication date: April 8, 2010
    Applicant: CHIPPAC, INC.
    Inventors: Hee-Bong Lee, Hyun-Joon Oh
  • Patent number: 7692279
    Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: April 6, 2010
    Assignee: Chippac, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Patent number: 7691681
    Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has interconnection between the active site of the die and the die paddle. Also, methods for making the package are disclosed.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: April 6, 2010
    Assignee: ChipPAC, Inc.
    Inventor: Cheonhee Lee
  • Patent number: 7690551
    Abstract: A die attach process employs a temperature gradient lead free soft solder metal sheet or thin film as the die attach material. The sheet or thin film is formed to a uniform thickness and has a heat vaporizable polymer adhesive layer on one surface, by which the thin film is laminated onto the back metal of the silicon wafer. The thin film is lead-free and composed of acceptably non-toxic materials. The thin film remains semi-molten (that is, not flowable) in reflow temperatures in the range about 260° C. to 280° C. The polymer adhesive layer is effectively vaporized at the high reflow temperatures during the die mount.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: April 6, 2010
    Assignee: ChipPAC, Inc.
    Inventor: Ong You Yang
  • Patent number: 7682873
    Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-down flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7678611
    Abstract: A semiconductor spacer structure comprises in order a backgrinding tape layer, a spacer adhesive layer, a semiconductor spacer layer, an optional second spacer adhesive layer, a dicing tape layer. In a first method a spacer wafer having first and second sides, a backgrinding tape layer and a spacer adhesive layer between the first side and the backgrinding tape layer, is obtained. The second side is background and secured to a dicing tape. The backgrinding tape is removed and the resulting structure is diced to create spacer/adhesive die structures. A second method backgrinds the second side with the backgrinding tape layer at the first side. A protective cover layer is secured to the second side with a spacer adhesive layer therebetween. The backgrinding tape layer is removed and the remaining structure is secured to a dicing tape with the protective cover layer exposed. The protective cover layer is removed and the resulting structure is diced thereby creating spacer/adhesive die structures.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: March 16, 2010
    Assignee: ChipPAC, Inc.
    Inventor: Seung Wook Park