Patents Assigned to Cirrus Logic, Inc.
  • Patent number: 11456704
    Abstract: In accordance with embodiments of the present disclosure, a system may include a circuit having a power converter and an amplifier, wherein the power converter is configured to generate an intermediate voltage, provide the intermediate voltage as an amplifier supply voltage to the amplifier, and share the intermediate voltage with one or more additional circuits external to the circuit, wherein at least one of the one or more additional circuits is configured to generate the intermediate voltage.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: September 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Jeffrey Allen May, Eric J. King, Firas Azrai
  • Patent number: 11457312
    Abstract: A device may include a housing, a transducer coupled to the housing for reproducing an audio signal including both a source audio signal for playback to a listener and an anti-noise signal for countering the effects of ambient audio sounds in an acoustic output of the transducer, an error microphone coupled to the housing in proximity to the transducer for providing an error microphone signal indicative of the acoustic output of the transducer and the ambient audio sounds at the transducer, and a processing circuit.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: Sandeep P. Sira
  • Patent number: 11455002
    Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Neil Whyte, Andy Brewster, Angus Black
  • Patent number: 11450630
    Abstract: Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 20, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: Christopher Healy
  • Patent number: 11450097
    Abstract: Described embodiments relate to a method operable in a biometric authentication system. The method comprises initiating generation of an acoustic stimulus for application to a user's ear; and determining a quality measure of a response signal to the acoustic stimulus. Responsive to determining that the quality measure is inadequate for performing a biometric process, the method comprises one or more of: (i) modifying one or more properties of the acoustic stimulus to improve a signal to noise ratio, SNR, of the response signal and (ii) cancelling the effect of noise from outside the ear on the response signal of the user's ear to the acoustic stimulus to improve the SNR of the response signal.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 20, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Thomas Ivan Harvey, Vitaliy Sapozhnykov, Brenton Potter
  • Patent number: 11451898
    Abstract: A method and device for detecting whether a headset is on ear. A probe signal is generated for acoustic playback from a speaker. A microphone signal from a microphone is received, the microphone signal comprising at least a portion of the probe signal as received at the microphone. The microphone signal is passed to a state estimator, to produce an estimate of at least one parameter of the portion of the probe signal contained in the microphone signal. The estimate of the at least one parameter is processed to determine whether the headset is on ear.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: September 20, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Vitaliy Sapozhnykov, Thomas Ivan Harvey, Nafiseh Erfaniansaeedi, Robert Luke
  • Patent number: 11451215
    Abstract: A piece-wise linear (PWL) waveform generator includes a current generator that generates a reference current, an output capacitor across which an output voltage is developed to form a PWL waveform, charging and discharging current sources for charging/discharging the output capacitor based on the reference current, a clock-controlled switch network for controlling the charging/discharging of the output capacitor, and a feedback control loop that senses the output voltage and controls the current generator to vary the reference current based on the output voltage. A first switch controlled by a first clock signal periodically connects/disconnects a current source output to/from a load impedance and a second switch controlled by a second clock signal periodically connects/disconnects a capacitor to/from the current source while disconnected from the load impedance.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: September 20, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Miao Song, Xin Zhao, Tejasvi Das, Jason Wardlaw, Michael A. Kost
  • Patent number: 11437022
    Abstract: A method of speaker recognition comprises receiving an audio signal representing speech. A speaker change detection process is performed on the received audio signal. A trigger phrase detection process is also performed on the received audio signal. On detecting the trigger phrase in the received audio signal, a speaker recognition process is performed on the detected trigger phrase and on any speech preceding the detected trigger phrase and following an immediately preceding speaker change.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11437021
    Abstract: The application describe a data processing system and associated methods for processing received speech data. The data processing system comprises: a classification unit configured to receive data derived from an audio signal and, based on the received data, to determine a classification state of an acoustic environment; wherein access to a subsequent processing unit is controlled based on the classification state of the acoustic environment. The classification state may be derived based on a pre-trained model, wherein the representation comprises a representation of the direct to reverberant ratio (DRR) of the audio signal.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: Zhengyi Xu
  • Patent number: 11438697
    Abstract: A system may include a digital delta-sigma modulator configured to receive a digital audio input signal and quantize the digital audio input signal into a quantized signal, a filter configured to receive the quantized signal and perform filtering on the quantized signal to generate a filtered quantized signal, the filter having a variable group delay, and a current-mode digital-to-analog converter configured to receive the filtered quantized signal and convert the filtered quantized signal into an equivalent current-mode analog audio signal.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John L. Melanson, Wai-Shun Shum, Leyi Yin
  • Patent number: 11437935
    Abstract: A method may include controlling commutation of a plurality of switches of an output stage comprising the plurality of switches in order to transfer charge between an energy storage device and a load to generate an output voltage across the load as an amplified version of an input signal, wherein the load comprises capacitive energy storage and controlling the power converter in order to regulate a cumulative electrical energy present in the system at an energy target, wherein the power converter is configured to transfer electrical energy from a source of electrical energy coupled to an input of the power converter to the energy storage device coupled to the output of the power converter and configured to store the electrical energy transferred from the source of electrical energy.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric J. King, John L. Melanson
  • Patent number: 11438694
    Abstract: An integrated circuit for digital signal routing. Signal routing is achieved with a multiply-accumulate block, which takes data from one or more data sources and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Graeme Gordon Mackay, Jonathan Timothy Wigner, Gordon Richard McLeod
  • Patent number: 11435412
    Abstract: This applications relates to methods and apparatus for monitoring a socket (101), to detect a connection status of a mating plug (102), e.g. for monitoring an audio jack socket for connection of an audio jack plug. A monitor (115, 305) is configured to monitor a voltage (VM) at a monitoring node (114), which is coupled to a jack detect contact (112) of the socket and a voltage pull-up element (113). The voltage (VM) at the monitoring node (114) is monitored against a threshold (Vthv) and a threshold module (302) is configured to vary the threshold depending on an indication of signal activity (SACT) of a signal path for a first socket contact (103) which will be electrically connected to the jack detect contact when a plug when inserted in the socket.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Bruce Bowlerwell
  • Patent number: 11431310
    Abstract: A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 30, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Amar Vellanki, Tejasvi Das, John L. Melanson
  • Patent number: 11431345
    Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT). The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 30, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11424682
    Abstract: A system for controlling a current in a power converter may include an outer control loop configured to use an outer set of output voltage thresholds for an output voltage generated by the power converter in order to provide hysteretic control of the current, an inner control loop configured to use an inner set of output voltage thresholds for the output voltage in order to provide continuous control of the current, the inner control loop further configured to measure a time duration required for the output voltage to cross a single pair of two output voltage thresholds of the inner set of output voltage thresholds in order to determine an input-referred estimate of a current load of the power converter and set a peak current threshold and a valley current threshold for the current based on the input-referred estimate of the current load.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 23, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Jason W. Lawrence, Eric J. King, Graeme G. Mackay, Theodore M. Burk
  • Patent number: 11423872
    Abstract: A system that reproduces an output signal including dynamic range enhancement (DRE) reduces audible artifacts generated by changes in operating range of the dynamic range enhancement (DRE) when the output signal includes an adaptive noise canceling (ANC) component. A first detection circuit determines an input signal amplitude and a second detection circuit determines a measure of an amplitude of a noise canceling component of the input signal. A control circuit determines whether the amplitude of the noise canceling component is significant with respect to the input signal amplitude and controls characteristics of a dynamic range enhancer to override a default behavior of the dynamic range enhancer if the amplitude of the noise-canceling component is significant with respect to the input signal amplitude. The characteristics may include rise/fall times of a gain control of the dynamic range enhancer and may be controlled in multiple separate frequency bands.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 23, 2022
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Ku He, Xiaofan Fei
  • Patent number: 11417349
    Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Peter John Frith, John Laurence Pennock
  • Patent number: 11418184
    Abstract: A system may include a sensor configured to output a sensor signal indicative of a distance between the sensor and a mechanical member associated with the sensor, a measurement circuit communicatively coupled to the sensor and configured to determine a physical force interaction with the mechanical member based on the sensor signal, and a compensator configured to monitor the sensor signal and to apply a compensation factor to the sensor signal to compensate for changes to properties of the sensor based on at least one of changes in a distance between the sensor and the mechanical member and changes in a temperature associated with the sensor.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: August 16, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Matthew Beardsworth, Tejasvi Das, Siddharth Maru, Luke Lapointe
  • Patent number: 11418153
    Abstract: This application relates to amplifier circuitry and, in particular, to class-D amplifier circuits. The application describes amplifier circuitry (400) for receiving an input signal (Sin) and generating first and second driving signals (SoutP, SoutN) for driving a bridge-tied-load. The amplifier circuitry includes first and second class-D output stages (403p, 403n) for generating the first and second driving signals based on the input signal. A controller (406) controllably varies a common-mode component of the first and second driving signals based on an indication of amplitude of the first and second driving signals. The controller varies the common-mode component, at lower signal amplitudes, so the common-mode level of the first and second driving signals is moved away from an operating region that leads to distortion.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: John P. Lesso, Andrew J. Howlett