Patents Assigned to Cirrus Logic, Inc.
  • Patent number: 11835554
    Abstract: The present application relates to current sensing circuitry (100) that comprises a differential amplifier (110) comprising first and second inputs configured to sense a current across a sense resistance, and an output configured to output a current sense signal. The circuitry (100) further comprises a first current source, a second current source and a switch network operable in: a first phase in which the first current source is connected to the first input and disconnected from the output, and the second current source is connected to the output and disconnected from the first input; and a second phase in which the first current source is connected to the output and disconnected from the first input, and the second current source is connected to the first input and disconnected from the output.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: December 5, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Dipankar Nag, Peter Hsu, Kapil R. Sharma, Gordon J. Bates, Simon R. Foster, Mark J. McCloy-Stevens
  • Patent number: 11837956
    Abstract: A method for determining if an inductor coupled to a switching network has been electrically shorted may include applying a voltage across the inductor for a predetermined period of time, controlling an impedance in an electrical path of a voltage source generating the voltage and the inductor, sensing an inductor current through the inductor, comparing the inductor current with a predetermined current threshold, and determining whether the inductor has been electrically shorted based on the inductor current, the predetermined current threshold, and the predetermined period of time.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: December 5, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Hasnain Akram, Graeme G. Mackay, Lingli Zhang, Ruoxin Jiang, Sakkarapani Balagopal, Theodore M. Burk
  • Patent number: 11832523
    Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer. The circuitry may be implemented as an integrated circuit and comprises driver circuitry configured to supply a drive signal to the piezoelectric transducer to cause the transducer to generate an output signal and active inductor circuitry configured to be coupled with the piezoelectric transducer. The active inductor circuitry may be tuneable to adjust a frequency characteristic of the output signal.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: November 28, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: John P. Lesso
  • Patent number: 11829461
    Abstract: The present invention relates to methods, apparatus and systems for audio playback via a personal audio device following a biometric process. A personal audio device may be used to obtain ear model data for authenticating a user via an ear biometric authentication system. Owing to that successful authentication, the electronic device is informed of the person who is listening to audio playback from the device. Thus the device can implement one or more playback settings which are specific to that authorised user.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: November 28, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: John Paul Lesso, John Forsyth
  • Patent number: 11831311
    Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 28, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: John Laurence Pennock, John Paul Lesso
  • Patent number: 11828885
    Abstract: Embodiments of the present disclosure provide apparatus, methods and computer programs for ultrasonic proximity-detection.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 28, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Pablo Peso Parada, Rahim Saeidi
  • Patent number: 11821761
    Abstract: A system may include a resistive-inductive-capacitive sensor configured to sense a physical quantity, and a measurement circuit communicatively coupled to the resistive-inductive-capacitive sensor and configured to measure one or more resonance parameters associated with the resistive-inductive-capacitive sensor and indicative of the physical quantity and, in order to maximize dynamic range in determining the physical quantity from the one or more resonance parameters, dynamically modify, across the dynamic range, either of reliance on the one or more resonance parameters in determining the physical quantity or one or more resonance properties of the resistive-inductive-capacitive sensor.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 21, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Tejasvi Das, Siddharth Maru, John L. Melanson
  • Patent number: 11817833
    Abstract: This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: November 14, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: John P. Lesso
  • Patent number: 11814284
    Abstract: The application relates to structures, e.g. substrates for supporting semiconductor die. The substrate defines a frame which lateral surrounds one or more die and is provided in contact with at least one side surface of the die, wherein the frame defines upper and lower surfaces of the substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 14, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Roberto Brioschi, Rkia Achehboune
  • Patent number: 11815534
    Abstract: This invention relates to current sensing, in particular for a signal processing circuit (500) for outputting an output signal (Sout) based on an input signal (Sin). An output stage (101) includes an output transistor (102) driven, in use, by a drive signal. A current monitor (501) is configured to monitor, in use, a first current through the output transistor, wherein the current monitor comprises a current sensor (105) having a sense transistor (106) configured to be driven based on the drive signal so as to generate a sense current related to the first current. A compensation controller (301) receives an indication of signal level of the input signal and controllably varies operation of the current monitor (501) so as to at least partially compensate for signal-dependent variation in a relationship between the first current and the first sense current.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 14, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Tahir Rashid, Mehul Mistry
  • Patent number: 11808669
    Abstract: A system may include a resonant sensor configured to sense a physical quantity, a measurement circuit communicatively coupled to the resonant sensor and configured to measure one or more resonance parameters associated with the resonant sensor and indicative of the physical quantity using an incident/quadrature detector having an incident channel and a quadrature channel and perform a calibration of a non-ideality between the incident channel and the quadrature channel of the system, the calibration comprising determining the non-ideality by controlling the sensor signal, an oscillation signal for the incident channel, and an oscillation signal for the quadrature channel; and correcting for the non-ideality.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Tejasvi Das, Siddharth Maru, John L Melanson
  • Patent number: 11811370
    Abstract: A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Ramin Zanbaghi, Lingli Zhang, Wei Xu, Justin Richardson, John L. Melanson
  • Patent number: 11809334
    Abstract: An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Neil Whyte, Michael Chandler-Page, Pradeep Saminathan, Jon Eklund
  • Patent number: 11812218
    Abstract: A system may include a vibrating surface, a single mechanical transducer mechanically coupled to the vibrating surface, a signal processing subsystem configured to receive an audio signal and a haptic signal, process the audio signal and the haptic signal to generate a combined audio-haptic signal, and drive the combined audio-haptic signal to the single mechanical transducer in order to generate concurrent audio playback and haptic effects on the vibrating surface; and a control subsystem configured to, responsive to a haptic stimulus, modify at least one parameter of at least one of the audio signal and the haptic signal to accommodate the concurrent audio playback and haptic effects on the vibrating surface within at least one operational limit of the system.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Philip Clarkin, Itisha Tyagi, Kaichow Lau
  • Patent number: 11810544
    Abstract: Embodiments generally relate to a signal processing device for on ear detection for a headset. The device comprises a first microphone input for receiving a microphone signal from a first microphone, the first microphone being configured to be positioned inside an ear of a user when the user is wearing the headset; a second microphone input for receiving a microphone signal from a second microphone, the second microphone being configured to be positioned outside the ear of the user when the user is wearing the headset; and a processor.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: Brenton Steele
  • Patent number: 11811312
    Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: November 7, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: John P. Lesso, Peter J. Frith, John L. Pennock
  • Patent number: 11803742
    Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: October 31, 2023
    Assignee: Cirrus Logic Inc.
    Inventor: John Paul Lesso
  • Patent number: 11804813
    Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (?) from the output signal and the input signal. In various embodiments the extent to which the error signal (?) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: October 31, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 11799657
    Abstract: There is described a system and method for performing biometric authentication, preferably voice biometric authentication. The system has a host device such as a mobile phone and a coupled headset device. The headset device is arranged to receive audio, and to cryptographically protect the audio before transmission to the host device for verification and biometric authentication.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 24, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Michael Page, John Paul Lesso
  • Patent number: 11799428
    Abstract: A method may include receiving, by a calibration circuit, an output of a subsystem comprising the sensor and the analog front end. The method may further include separating the output individually into the sensor offset and the amplifier offset by using inherent properties of separate frequency ranges for the sensor offset and the amplifier offset. The method may also include calibrating, by the calibration circuit, the sensor offset by determining a first calibration value for the sensor offset such that the output approximates zero during an idle-channel condition. The method may additionally include calibrating, by the calibration circuit, the amplifier offset by determining a second calibration value for the amplifier offset such that the output approximates zero during the idle-channel condition.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 24, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Saurabh Singh, Chandra B. Prakash