Patents Assigned to Cirrus Logic, Inc.
  • Patent number: 12164925
    Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 10, 2024
    Assignee: Cirrus Logic, Inc.
    Inventors: Nariankadu D. Hemkumar, Christopher Jackson, Younes Djadi, Nathan Daniel Pozniak Buchanan
  • Patent number: 12166502
    Abstract: The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.
    Type: Grant
    Filed: January 22, 2024
    Date of Patent: December 10, 2024
    Assignee: Cirrus Logic Inc.
    Inventor: Gavin Mcveigh
  • Patent number: 12166457
    Abstract: Amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include multiple driver circuits and a control circuit. The control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits, according to an input signal to be reproduced by one or more of the multiple amplifier driver circuits. The control circuit determines a splice point at which the control circuit selects between actively operating selected ones of the multiple driver circuits or all of the multiple driver circuits.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: December 10, 2024
    Assignee: CIRRUS LOGIC, INC.
    Inventors: John L. Melanson, Cory J. Peterson, Chandra Prakash, Ramin Zanbaghi, Eric Kimball
  • Patent number: 12163984
    Abstract: Accurate operation of a current monitor is provided by injecting a bias voltage to a maintain de-selected sense amplifier input in an active state. An electronic system includes an output stage to supply a load current and includes two push-pull output drivers having sense resistors supplying a first and a second sense voltage. An included mode control circuit selects between a first and a second operating mode and selects a polarity of the current. An included current monitor receives the sense voltages and has a control input coupled to the mode selection control circuit. The current monitor provides an output that is dependent on both sense voltages in the first operating mode and is indicative of one of the sense voltages selected according to the selected polarity in the second operating mode. The bias voltage is injected into an unselected sense inputs to maintain active operation of the sense amplifier.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 10, 2024
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Vamsikrishna Parupalli, Gaurav Agarwal, John L Melanson
  • Patent number: 12167696
    Abstract: The present disclosure relates to circuitry for driving a piezoelectric transducer to generate an audio output. The circuitry comprises pre-processor circuitry configured to process an input audio signal to generate a processed signal; driver circuitry coupled to the pre-processor circuitry and configured to generate a drive signal, based on the processed signal, for driving the piezoelectric transducer; and processor circuitry configured to determine a resonant frequency of the piezoelectric transducer. The pre-processor circuitry is configured to process the input audio signal based on the determined resonant frequency so as to generate the processed signal.
    Type: Grant
    Filed: January 11, 2024
    Date of Patent: December 10, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: John P. Lesso, Anthony S. Doy
  • Patent number: 12159528
    Abstract: A method for determining and mitigating over-excursion of an internal mass of an electromechanical transducer may include measuring a sensed signal associated with the electromechanical transducer in response to a driving signal driven to the electromechanical transducer, determining a non-linearity value based on the sensed signal, mapping the non-linearity value to a probability of over-excursion of the internal mass, and applying a gain to a signal path configured to generate the driving signal based on the probability.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: December 3, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Marco A. Janko, Filippo Rossi, Hamid Sepehr, Kyle Wilkinson, Emmanuel A. Marchais, Vadim Konradi, Anil Lal, Aleksey S. Khenkin, Chin Huang Yong
  • Patent number: 12160248
    Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 3, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Vamsikrishna Parupalli, Mikel Ash, Jianping Wen, Melvin L. Hagge
  • Patent number: 12158687
    Abstract: A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: December 3, 2024
    Assignee: Cirrus Logic, Inc.
    Inventors: Sachin Deo, Nariankadu D. Hemkumar, Akhilesh Persha, Younes Djadi
  • Patent number: 12160166
    Abstract: A driver apparatus for driving a load with a differential drive signal is described. For a level of input signal within a first range, a first switching driver modulates the voltage at a first output node with a first modulation index by switchably connecting at least one flying capacitor to the first output node, whilst a second switching driver modulates the voltage at a second output node with a second modulation index by controlling switching between DC voltages that are maintained throughout a switching cycle of the driver apparatus. The first and second switching drivers are controlled so, for at least a first part of the first input range, a change in input signal level results in a change of the first controlled modulation index that has a different magnitude to any change in the second controlled modulation index, a constant modulation frequency of the differential drive signal is maintained.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: December 3, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Lingli Zhang, Yongjie Cheng, John L. Melanson
  • Patent number: 12155380
    Abstract: This application relates to methods and apparatus for driving a transducer connected between two output nodes in a bridge-tied-load configuration. A driver receives first and second supply voltages and has charge pumps that generate respective first and second boosted voltages. The driver is operable in a first driver mode in which each output node is modulated between the first and second supply voltage; a second driver mode in which one output nodes is modulated between the first and second supply voltages and the other output node is modulated between either the first boosted voltage and the first supply voltage or between the second supply voltage and the second boosted voltage; and a third driver mode in which one of the output nodes is modulated between the first supply voltage and the first boosted voltage and the other output node is modulated between the second supply voltage and the second boosted voltage.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: November 26, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Ross C. Morgan, Yongjie Cheng, Lingli Zhang
  • Patent number: 12155299
    Abstract: A power converter for converting an input voltage at an input of the power converter into an output voltage at an output of the power converter may include a first power converter branch comprising a first capacitor, a first switch network, and a first inductor, the first switch network arranged to selectably couple the first capacitor between an input voltage, a first reference voltage, and a first terminal of the first inductor, wherein a second terminal of the first inductor is coupled to an output node; a second power converter branch comprising a second capacitor, a second switch network, and a second inductor, the second switch network arranged to selectably couple the second capacitor between the input voltage, a second reference voltage, and a first terminal of the second inductor, wherein a second terminal of the second inductor is coupled to the output node; and a third switch network between the first power converter branch and the second power converter branch, wherein the third switch network is
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: November 26, 2024
    Assignee: Cirrus Logic Inc.
    Inventor: Changjong Lim
  • Patent number: 12149899
    Abstract: Circuitry for acoustic crosstalk cancellation between first and second acoustic signals, the circuitry comprising: crosstalk cancellation circuitry configured to: receive a first audio signal and, based on the received first audio signal, generate a first crosstalk cancellation signal; receive a second audio signal and, based on the received second audio signal, generate a second crosstalk cancellation signal; combine the first crosstalk cancellation signal with a signal indicative of the second audio signal to generate a first crosstalk cancellation circuitry output signal; and combine the second crosstalk cancellation signal with a signal indicative of the first audio signal to generate a second crosstalk cancellation circuitry output signal; and output stage circuitry configured to: receive the first crosstalk cancellation circuitry output signal and, based on the received first crosstalk cancellation circuitry, generate a first drive signal for driving a first speaker to generate the first acoustic signal
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: November 19, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Dayong Zhou, Brad Zwernemann, Kaichow Lau, Dana J. Taipale, John L. Melanson
  • Patent number: 12149895
    Abstract: A method in a biometric authentication system, generating an acoustic stimulus for application to a user's ear; receiving an audio signal representing a response of the user's ear canal to the acoustic stimulus; adapting an ear canal response estimate of the user's ear canal to the acoustic stimulus to reduce an error between the audio signal and the ear canal response estimate; calculating one or more quality metrics, the quality metrics comprising one or more of: an ear canal response estimate quality metric comprising one or more energy characteristics of the ear canal response estimate; an error quality metric derived from the error; an audio response quality metric comprising one or more statistical characteristics of the audio signal; and determining a validity of the audio signal for use in a biometric process based on the quality metrics.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: November 19, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: William E. Sherwood, Cedric Andrieu, Ghassan Maalouli, Khaled Lakhdhar
  • Patent number: 12149256
    Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT) The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 19, 2024
    Assignee: Cirrus Logic Inc.
    Inventor: John P. Lesso
  • Patent number: 12144606
    Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: November 19, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: John P. Lesso, Yanto Suryono, Toru Ido
  • Patent number: 12143078
    Abstract: A method for matching a pair of composite circuit elements (CEs) included in a circuit includes fabricating N CEs (e.g., resistors, transistors, current sources, capacitors) designed to match and switches configurable, according to M different combinations, to connect N/2 of the N CEs to form a first composite CE and to connect a remaining N/2 of the N CEs to form a second composite CE. Sequentially in time, for each combination of the M combinations, the switches are configured to form the first and second composite CEs according to the combination and a characteristic of the circuit is measured that includes the formed first and second composite CEs. The characteristic indicates how well the formed composite CEs match. A final combination of the M combinations is chosen whose measured characteristic indicates a best match and the final combination is used to configure the switches to form the composite CEs.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: November 12, 2024
    Assignee: Cirrus Logic, Inc.
    Inventors: Edmund M. Schneider, Ramin Zanbaghi, Terence C. Bowness, Eric Kimball
  • Patent number: 12142259
    Abstract: A method of detecting live speech comprises: receiving a signal containing speech; obtaining a first component of the received signal in a first frequency band, wherein the first frequency band includes audio frequencies; and obtaining a second component of the received signal in a second frequency band higher than the first frequency band. Then, modulation of the first component of the received signal is detected; modulation of the second component of the received signal is detected; and the modulation of the first component of the received signal and the modulation of the second component of the received signal are compared. It may then be determined that the speech may not be live speech, if the modulation of the first component of the received signal differs from the modulation of the second component of the received signal.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: November 12, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 12143713
    Abstract: A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: November 12, 2024
    Assignee: Cirrus Logic, Inc.
    Inventors: Younes Djadi, Nariankadu D. Hemkumar, Sachin Deo, Daniel T. Bogard, Nathan Daniel Pozniak Buchanan, Eric B. Smith
  • Patent number: 12135774
    Abstract: Embodiments of the invention relate to methods, apparatus and systems for biometric processes. The methods include updating stored ear model data for a user following successful authentication of the user. The ear model data may be acquired using a personal audio device that generates an acoustic stimulus and detects a measured response. The acquisition of the ear model data may be responsive to a determination that the personal audio device is inserted into or placed adjacent to the user's ear. The acquisition of the ear model data may also be responsive to the determination that the personal audio device has not been removed from or moved away from the user's ear.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: November 5, 2024
    Assignee: Cirrus Logic Inc.
    Inventor: John Paul Lesso
  • Patent number: 12132493
    Abstract: A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: October 29, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Arashk Norouzpourshirazi, Ramin Zanbaghi, Stephen T. Hodapp, Christophe J. Amadi, Ravi K. Kummaraguntla, Dhrubajyoti Dutta