Abstract: A method for minimizing undesired movement of a moving mass of an electromagnetic load may include detecting undesired movement of the moving mass based on real-time measurements of one or more parameters associated with the electromagnetic load and, responsive to detecting undesired movement of the moving mass, affecting a signal applied to the moving mass to reduce the undesired movement.

Abstract: A method for diagnosing a condition of a first headset enclosed in a headset enclosure. The method comprises playing a first audio stimulus through a first speaker of the headset; detecting a first response signal derived by a first transducer; and determining a condition of the first speaker and/or first transducer based on the first response signal.

Abstract: A method for constructing a solenoid inductor of an IC package with active/passive devices includes positioning an inner winding substantially around a magnetic core, positioning an outer winding substantially around the inner winding, and using a layered process to perform positioning the inner and outer windings. The layered process includes processing a first conducting layer as a bottom layer of the outer winding, above processing a first dielectric layer, above processing a second conducting layer as a bottom layer of the inner winding, above processing a second dielectric layer, above processing a magnetic core layer, above processing a third dielectric layer, above processing a third conducting layer as a top layer of the inner winding, above processing a fourth dielectric layer, above processing a fourth conducting layer as a top layer of the outer winding, above processing a fifth dielectric layer, and the inner and outer windings are electrically connected.

Abstract: A system for generating a plurality of switch control signals of a multiphase power converter may include a plurality of inputs, each input of the plurality of inputs configured to receive a respective control signal for controlling a respective phase of the multiphase power converter, and a plurality of control paths comprising a control path for each respective control signal, each control path configured to, for its respective control signal, control a switching period of the respective control signal for such control path based on a measure of alignment among the respective control signal for such control path and the other respective control signals of the other control paths.

Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

Abstract: Current detection circuitry for generating an average inductor current signal indicative of an average inductor current during an operational cycle of power converter circuitry, the current detection circuitry comprising: circuitry for generating a peak inductor current signal indicative of a peak inductor current during the operational cycle; and circuitry for applying a ripple current estimate signal, indicative of an estimate of half of a ripple current in the power converter circuitry, to the peak inductor current signal to generate the average inductor current signal, wherein the ripple current is equal to a difference between the average inductor current and the peak inductor current.

Abstract: Embodiments described herein relate to methods and apparatus for outputting a haptic signal to a haptic transducer. A method for triggering a haptic signal being output to a haptic transducer comprises receiving an audio signal for output through an audio output transducer; determining whether the audio signal comprises a haptic trigger based on an indication of a rate of change of an amplitude of the audio signal, and responsive to determining that the audio signal comprises a haptic trigger, triggering the haptic signal to be output to the haptic transducer.

Abstract: A power converter for converting an input voltage at an input of the power converter into an output voltage at an output of the power converter may include a switching node, a power inductor coupled between the switching node and the output, a flying capacitor having a first flying capacitor terminal and a second flying capacitor terminal, a pump capacitor having a first pump capacitor terminal and a second pump capacitor terminal, the second pump capacitor terminal coupled to ground, a first switch coupled between the input and the first flying capacitor terminal, a second switch coupled between the first flying capacitor terminal and the switching node, a third switch coupled between the second flying capacitor terminal and the switching node, a fourth switch coupled between the second flying capacitor terminal and a ground voltage, a fifth switch coupled between the second flying capacitor terminal and the first pump capacitor terminal, and a sixth switch coupled between the output and the first pump capac

Abstract: A power management system for use in a device comprising a battery and one or more components configured to draw electrical energy from the battery may include a first power converter configured to electrically couple between charging circuitry configured to provide electrical energy for charging the battery and the one or more downstream components and a bidirectional power converter configured to electrically couple between the charging circuitry and the battery, wherein the bidirectional power converter is configured to transfer charge from the battery or transfer charge from the battery based on a power requirement of the one or more components and a power available from the first power converter.

Abstract: A switching transducer driver operable in: a first mode in which first and second output stage switches are controlled to generate a two-level output signal, wherein an impedance of the first output stage switch is substantially the same as an impedance of the second output stage switch; and a second mode in which the first and second output stage switches and a third switch are controlled to generate a three-level output signal, wherein an impedance of the third switch is substantially greater than the impedance of the first output stage switch and the second output stage switch.

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Abstract: A method for enforcing design rules in a circuit layout may include providing a circuit schematic for an integrated circuit to a circuit simulator, wherein the circuit layout is derived from a circuit schematic, using the circuit simulator to simulate the circuit schematic and generate simulated electrical parameters for the integrated circuit, and using the simulated electrical parameters to enforce physical design rules when generating the circuit layout based on the simulated electrical parameters.

Abstract: A speech recognition system comprises: an input, for receiving an input signal from at least one microphone; a first buffer, for storing the input signal; a noise reduction block, for receiving the input signal and generating a noise reduced input signal; a speech recognition engine, for receiving either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block; and a selection circuit for directing either the input signal output from the first buffer or the noise reduced input signal from the noise reduction block to the speech recognition engine.

Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.

Abstract: A system for estimating parameters of an electromagnetic load may include an input for receiving an input excitation signal to the electromagnetic load, a broadband content estimator that identifies at least one portion of the input excitation signal having broadband content, and a parameter estimator that uses the at least one portion of the input excitation signal to estimate and output one or more parameters of the electromagnetic load.

Abstract: Circuitry for driving a transducer for an object detection system, the circuitry comprising drive circuitry configured to generate a drive waveform for the transducer, current monitor circuitry for monitoring a current through the transducer, and system identification circuitry. The system identification circuitry is configured to determine a characteristic of the transducer based on a first signal indicative of a drive voltage for the transducer and a second signal indicative of the current through the transducer. The circuitry is operative to adjust the drive waveform based on the determined characteristic of the transducer.

Abstract: A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

Abstract: This application relates to voltage regulators and, particular, to low-dropout regulators (LDOs). The regulator (300) has an output stage (102) which receives an input voltage (Vin) and outputs an output voltage (Vout) and which includes at least one transistor (103) as an output device configured to pass an output current to the output, based on a drive voltage (V1). A differential amplifier (101) is configured to receive a feedback signal derived from the output voltage and also a reference voltage (REF) to generate an amplifier output to control the drive voltage (V1) to minimise any difference between the feedback signal and the reference voltage. A controller (301) is operable to selectively reconfigure the output stage to provide a change in output current in response to a load activity signal (ACT), which is indicative of a change in load activity that results in a change in load current demand for a load connected, in use, to the output.

Abstract: A system may include amplifier circuitry configured to drive an electromagnetic load with a driving signal and a processing system communicatively coupled to the electromagnetic load and configured to compensate for current-sensing error of the processing system caused by feedback circuitry of the amplifier circuitry.

Abstract: A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.