Patents Assigned to Compaq Computer Corp.
  • Patent number: 6424953
    Abstract: An electronic commerce system and method includes a broker computer system having a database of scrips, a vendor computer, and a consumer computer system having a wallet protected by a pass phrase. To strengthen the pass phrase, the wallet adds a nonce and a random phrase having a length determined by the processing speed of the computer system. The internal phrase is hashed with another nonce to form a checksum, which is stored in the wallet. A portion of each scrip is encrypted by hashing a unique nonce and the internal pass phrase. XORing the scrip with the hash, and storing the encrypted portion and nonce in the wallet. The wallet adds another nonce and random string to form an internal pass phrase. To use the scrip, the user provides the pass phrase, The wallet verifies that the phrase is correct, and if so, decrypts the scrip.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: July 23, 2002
    Assignee: Compaq Computer Corp.
    Inventors: Steven C. Glassman, Mark S. Manasse
  • Patent number: 6421537
    Abstract: An improved home location register (HLR) that includes a switch capability mediation module for implementing switch capability mediation between different mobile switching centers (MSCs). According to the invention, when one MSC (home MSC of a receiving party) attempts to communicate with another MSC (serving MSC) via the HLR serving the home MSC, the mediation module determines whether the two MSCs are provided by different vendors and whether they implement different capabilities, based on the MPCM (MSC ID Point Code Map) file records of both the originating and serving MSCs. The MPCM files store MSCs' network configuration information.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: July 16, 2002
    Assignee: Compaq Computer Corp.
    Inventors: James A. Lamb, Pamela J. Jacobs
  • Patent number: 6408394
    Abstract: A computer is provided having a SCSI subsystem and multiple SCSI devices connected to that subsystem. Those devices involve electromechanical motors which require a greater amount of current during times needed to spin-up the motor-driven devices to a steady-state velocity than current needed to maintain that velocity. Each SCSI device includes an inquiry page indicating attributes of that device and whether that device supports fast spin-up. If a device supports fast spin-up, firmware within the computer is activated during ROM POST operations forwards a command to begin a spin-up operation on one SCSI device before the prior device has completed its spin-up operation. In this manner devices which support fast spin-up can concurrently spin-up to their constant velocity value so as to minimize the initialization process of the computer system subsequent to reset or boot-up of the system.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: June 18, 2002
    Assignee: Compaq Computer Corp.
    Inventors: Kerry B. Vander Kamp, Edward J. Chen
  • Patent number: 6356427
    Abstract: An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The technique uses an ESD protection circuit that includes a two cascode-connected clamps between the protected pad and a reference voltage conductor and two inverter amplifiers for driving the clamps. A control signal that used to control the amplifiers is derived from a high-voltage pad through voltage limiting transistors.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: March 12, 2002
    Assignee: Compaq Computer Corp.
    Inventor: Warren R. Anderson
  • Patent number: 6330528
    Abstract: An operating system is simulated to run in conjunction with a native operating system, allowing processes, particularly multi-threaded processes, originally developed for the simulated operating system to be ported to the environment of the native operating system with a minimum of effort. In their natural environment the processes being ported have the capability of requesting that other processes be terminated. This capability is provided in the simulated system and in a multi-threaded environment of the simulated system. Processes executing in the simulated system, even if multi-threaded, also have the capability of protecting against being stopped when executing critical code.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: December 11, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Cheng-Yu Huang, Siddhesh Jere, Jeffrey D. Merrick, Sudesh Saoji
  • Patent number: 6298425
    Abstract: Updating a single block of metadata is optimized into a single I/O operation. Resilience against single block failure and system crashes with a single or less than three I/O operations is provided. The present invention method and apparatus stores two copies of the metadata in two areas on disk. Each individual block of metadata in each area is duplicated as a doublet. The doublet provides two copies of a subject block to be written to disk as a single I/O. This enables metadata to survive a single block failure since such a failure only affects half of the doublet. Further, each block of metadata has header information including an indication of transaction and a part count. A transaction is not deemed committed until corresponding blocks of all parts are found.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: October 2, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Christopher Whitaker, Conor Morrison, Alan Gordon Dewar, James Hogg, Kevin Playford
  • Patent number: 6279062
    Abstract: In accordance with the present invention, a method and apparatus are provided for efficiently transmitting data between stages of a decompression pipeline by implementing a control store register for minimizing the amount of data that is transferred among decompression units. The control store register is a register having memory locations that are associated with decompressed coefficients. As the coefficients are decompressed, a determination is made as to whether they contain zero or non-zero values. The result of that determination is stored in the control store register such that the processor performing the inverse quantization and inverse discrete cosine operations only retrieves non-zero coefficients. Therefore, data transmission is performed in an efficient manner.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: August 21, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Matthew Adiletta, Robert Stepanian, Teresa Meng
  • Patent number: 6275885
    Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: August 14, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Kenneth T. Chin, Michael J. Collins, John E. Larson, Robert A. Lester
  • Publication number: 20010012999
    Abstract: A computerized apparatus for reducing the size of a dictionary used in a text-to-speech synthesis system are provided. In an initial phase, the method and apparatus determine if entries in the dictionary, each containing a grapheme string and a corresponding phoneme string, can be fully matched by using at least one rule set used to synthesize words to phonemic data. If the entry can be fully matched using rule processing alone, the entry is indicated to be deleted from the dictionary. In a second phase, the method and apparatus determine if the entry, considered as a root word entry, is required in the dictionary in order to support phoneme synthesis of other entries containing the root word entry, and if so, the root word entry is indicated to be saved in the dictionary.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 9, 2001
    Applicant: Compaq Computer Corp.,
    Inventors: Anthony J. Vitale, Ginger Chun-Che Lin, Thomas Kopec
  • Patent number: 6272651
    Abstract: A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads.
    Type: Grant
    Filed: August 17, 1998
    Date of Patent: August 7, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Kenneth T. Chin, Clarence Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert Allen Lester, Gary J. Piccirillo
  • Patent number: 6272580
    Abstract: A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registers are programmed during boot-up of the computer system by assigning a subset of peripheral devices, bus agents, requesters, or bus masters to either a high priority ring or a low priority ring, if two levels of arbitration are used. The status of a low priority device can be elevated to equal priority with a high priority device by assigning the low priority device to a high priority port within the high priority ring if certain circumstances occur. Namely, if data transfers to or from the low priority device are terminated, then the low priority device will be promoted to a high priority device so that it need not wait until after the all high priority device requests have been polled.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: August 7, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Jeff Stevens, Robert A. Lester, Phillip M. Jones, Jeff W. Wolford, Peter Lee
  • Patent number: 6263395
    Abstract: An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: July 17, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Patrick L. Ferguson, Paul B. Rawlins, David F. Heinrich, Robert L. Woods
  • Patent number: 6262823
    Abstract: In a system for communicating optically encoded data among a network of nodes, the nodes are connected to each other by optical transmit and receive fibers. Each node includes a laser, a transmitter, and a receiver connected to the transmitters of the other nodes by a fiber stretcher. The rate at which the laser generates light pulses is controlled by a frequency control signal supplied to an oscillator connected to the laser. The delay from the transmitters to the receivers is controlled by a phase control signal supplied to the fiber stretcher connected to the receive fiber. The transmitter connected to the transmit fiber selective delays the pulses into a plurality of time multiplexed channels. The receiver connected to the fiber stretcher selectively detects the pulses in the time multiplexed channels while all of the pulses of all of the nodes are globally synchronized in all of the time multiplexed channels in frequency and phase using the frequency and phase control signals.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: July 17, 2001
    Assignee: Compaq Computer Corp.
    Inventor: Andreas Georg Nowatzyk
  • Patent number: 6259435
    Abstract: A keyboard input device includes a processor repeatedly executing a scan routine to detect key press events while masking the events from an external monitoring means. The keyboard input device has a number of finger-activatable keys, each connected at the intersection of row signal lines and column signal lines, which are in turn connected to the processor. The processor systematically activates the rows and randomly activates the columns. A key press event causes the key's associated row and column to create a closed switch. The processor monitors the columns for a signal forced on pairs of rows. Obfuscating signals forced onto the columns inhibit detection of the key press event signals by an external source.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: July 10, 2001
    Assignee: Compaq Computer Corp.
    Inventor: Donald P. Matthews, Jr.
  • Patent number: 6249830
    Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: June 19, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Dale J. Mayer, Sompong Paul Olarig, William F. Whiteman, David F. Heinrich
  • Patent number: 6249756
    Abstract: An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: June 19, 2001
    Assignee: Compaq Computer Corp.
    Inventors: William Patterson Bunton, David A. Brown, David T. Heron, Charles Edward Peet, Jr., William Joel Watson, John C. Krause
  • Patent number: 6249879
    Abstract: A method and apparatus for transparent failover of a filesystem within a computer cluster is provided. For failover protection, a filesystem is physically connected to an active server node and a standby server node. A cluster file system provides distributed access to the filesystem throughout the computer cluster. The cluster file system monitors the progress of each operation performed on the failover protected filesystem. If the active server node should fail during an operation, all processes performing operations on the failover protected filesystem are caused to sleep. The filesystem is then relocated to the standby server node. The cluster file system then awakens each sleeping process and retries each pending operation.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: June 19, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Bruce J. Walker, John L. Byrne
  • Patent number: 6247139
    Abstract: A method and apparatus for transparent failover of a filesystem within a computer cluster is provided. For failover protection, a filesystem is physically connected to an active server node and a standby server node. A cluster file system provides distributed access to the filesystem throughout the computer cluster. The cluster file system monitors the progress of each operation performed on the failover protected filesystem. If the active server node should fail during an operation, all processes performing operations on the failover protected filesystem are caused to sleep. The filesystem is then relocated to the standby server node. The cluster file system then awakens each sleeping process and retries each pending operation.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: June 12, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Bruce J. Walker, John L. Byrne, William W. Chow, John A. Gertwagen, Laura L. Ramirez, David B. Zafman
  • Patent number: 6247109
    Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one operating system instance to another, allowing different loads in the system to be accommodated.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: June 12, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Frederick G. Kleinsorge, Stephen F. Shirron
  • Patent number: 6230225
    Abstract: A method and apparatus for broadcasting data to multiple target devices during a single bus transaction. Each of a plurality of potential target devices detect the beginning of a primary bus transaction and retrieve transaction command and target device identification information from a multicast bus. The transaction command information and target device identification information are decoded. A determination is made by each device as to whether the decoded target device identification information matches the identity of the device and furthermore whether the decoded transaction command is a read command. If the target device identification information matches the identity of the device and the command is a read, the device writes data present on the primary device into the device.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: May 8, 2001
    Assignee: Compaq Computer Corp.
    Inventors: Sompong P. Olarig, Thomas J. Bonola