Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract: A core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and either an AGP or PCI device(s). The core logic chip set also has an AGP/PCI arbiter having additional Request ("REQ") and Grant ("GNT") signal lines so that more than one PCI device may be utilized on the additional PCI bus. Selection of the type of bus bridge (AGP or PCI) in the core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or PCI device connected to the common bus.

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of peripheral component interconnect ("PCI") buses capable of operating at 66 MHz. Each of the plurality of PCI buses have the same logical bus number. The core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device connected to the plurality of PCI physical buses. Each of the plurality of PCI buses has its own read and write queues to provide transaction concurrency of PCI devices on different ones of the plurality of PCI buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used.

Abstract: A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

Abstract: A network (10) includes a repeater (12) that can service data devices that operate using different communications protocols. The data devices (18, 20, 22) couple to the ports (34) of the repeater (12), and operate using a first communications protocol in a first domain (14). The data devices (26, 28, 30) also couple to the ports (34) of the repeater (12) and operate using a second communications protocol in a second domain (16). Information on the operation of a port (34) may be displayed using one port indicator (202) or two port indicators (300, 302).

Abstract: A reset circuit for a computer system having PCI chip set, the reset circuit for resetting a PCI data bus in the event of a warm boot in the computer system to prevent corrupt data files, the reset circuit including a logical AND gate with a first input connected to a cold boot reset pin of the PMC, and an output connected to a PCI data bus; a logical OR gate with a first input connected to the flush pin of the PMC and an output connected to a second input of the logical AND gate; an inverter with an input connected to the flush pin of the PMC; and a delay device connected between an output of the inverter and a second input of the logical OR gate.

Abstract: To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

Abstract: A system for transferring data includes structure (i.e, hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second bus to the first bus, which structure includes substructure for waiting a programmably variable amount of time to see if additional data is requested by the first bus, before relinquishing control of the second bus.

Abstract: A computer system having an interconnection apparatus for interconnecting processors, peripherals, and memories, including a bus structure with an extended-bus portion and a non-extended-bus portion, and the extended-bus-compliant devices having a status register. The extended-bus-compliant devices are operable in either extended-bus mode involving both the extended-bus portion and non-extended-bus portion of the bus structure, or non-extended-bus mode involving only the non-extended-bus portion. Upon detecting a transmission error or device-related fault, the contents of the status register are altered so as to render the extended-bus-compliant devices operable in the non-extended-bus mode using only the non-extended-bus portion.

Abstract: A telephone system having a telephone network line for connection to an external phone line. The telephone system also includes a computer system and a telephone coupled to the telephone network line, and the telephone is taken off-hook to enter a voice command. A transmitter communicates the voice command from the telephone to the computer system without the telephone seizing the external phone line. A computer interface unit is connected to the computer system to receive the voice transmitted from the telephone and to transmit voice signals transmitted by the computer system to the telephone. A phone interface unit is connected between the telephone and telephone network line, and the phone interface unit is selectable between a first mode and a second mode. The phone interface unit connects the telephone to the telephone network line if it is in the first mode, and isolates the telephone from the telephone network line if it is in the second mode.

Abstract: In a computer system having a receiving computer and a source computer, a method for the remote flashing of the BIOS in the receiving computer including the steps of transferring the flash information from the source computer to the receiving computer, with the flash information including the flash code, the flash code instructions and an encrypted digital signature corresponding to the flash code. The receiving computer is operably placed in a secure mode. A hash value corresponding to the flash information is calculated, and the hash value from the flash information is decrypted. The flash code is validated by comparing the decrypted hash value of the flash information to the calculated hash value, and if validated, the BIOS if flashed with the new flash code.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST").

Abstract: An interactive apparatus for use with a computer, comprising a transceiver for two-way wireless communication with a plaything, the transceiver having terminals for connection to the computer, and a control device for causing the computer to send and receive information to and from the plaything via the transceiver to enable the plaything to provide interactive fantasy simulation of the behavior of a corresponding real-world object. In another aspect, the invention provides a method for enabling fantasy play using a computer and a plaything, comprising at the plaything, delivering output and receiving input associated with the fantasy play, and generating control signals at the computer for controlling the output based on the input, and by wireless communication sending the control signals from the computer to the plaything and sending the input from the plaything to the computer.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST").

Abstract: A network (10) includes several local networks (32, 34, 36). Each local network (32, 34, 36) includes a repeater (12, 16, 20) coupled to data devices (14, 18, 22). The combination of the repeater (12, 16, 20) and the data devices (14, 18, 22) form a collision domain for managing communications within the local network (32, 34, 36). Uplink modules (40, 44) manage communications between the local networks (32, 34, 36) by isolating collision domains and generating collision indications when messages cannot be transmitted. The uplink modules (40, 44) may also implement bridging, routing, or filtering capabilities that inhibit transmission of an intra-network message beyond its local network (32, 34, 36).

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: The present invention is a graphics subsystem with a plurality of storage elements addressed by multiple bit physical addresses and a video display with a plurality of pixels addressed by multiple bit logical addresses. The graphics subsystem includes an address conversion circuitry for converting the logical addresses of the pixels to physical addresses in the video memory. When the number of bytes needed to address the plurality of pixels across the screen is not equal to an integral power of two and the logical addresses of the plurality of pixels are arranged in tiles, the address conversion circuitry converts the logical addresses of the pixels to physical addresses in the video memory by converting only portions of the total address space into tiles at any one time.

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor.

Abstract: A PC system uses two different kinds of terminals both of which having different architecture from a traditional PC. A first kind of terminal receives and transmits high resolution information based on a relatively low resolution transmission link. This requires that software and intelligence be distributed between the PC and the terminal itself. A second kind of terminal device receives and transmits low bandwidth information, communicating with the PC or another terminal device, within a confined wireless network, or across another confined wireless network via a wired network. The device can be used within nanocells of coverage, and can move between the covered cells.