Abstract: A thermal management structure to provide mechanical isolation and heat removal for an unpackaged semiconductor die mounted directly on a printed circuit board substrate. The thermal management structure sandwiches the unpackaged semiconductor die and substrate between two heat sink pieces which are rigidly mounted to the substrate, thereby mechanically isolating the unpackaged semiconductor die and preventing the die from being accidentally touched. The two heat sink pieces further compliantly thermally engage selected sites on the exposed face of the semiconductor die and the surface of the substrate to conductively remove heat away from the substrate. The thermal management structure may also provide electromagnetic shielding which isolates the electromagnetic fields generated by the substrate from electromagnetic fields external to the thermal management structure.

Abstract: An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Abstract: A network switch for transferring packets of information including a plurality of shared packet buffers for a plurality of network ports. The network switch includes a switch matrix for providing independent input and output data channels between any one of the packet buffers and any of the network ports. The network switch further includes a switch controller for controlling transfer of data packets between the network ports and the packet buffers. In this manner, all of the packet buffers are shared and accessible by any of the network ports through the switch matrix. Each of the packet buffers stores only one data packet at a time, although the packet buffers may also be expanded to store multiple packets. The switch matrix includes an input switch with inputs coupled to the network ports and outputs coupled to the packet buffers and programmable crosspoint connections.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a remote peripheral component interconnect ("remote-PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and the remote-PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or a remote-PCI bus bridge is to be implemented. Selection of the type of bus bridge (AGP or remote-PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a remote-PCI device connected to the common AGP/remote-PCI bus.

Abstract: A layered block device driver for accessing a storage device coupled to a computer system having a platform on which a disk fault prediction application operates. The layered block device driver includes a file system driver coupled to the computer system, at least one upper level driver coupled to the file system driver, an intermediate driver having a first coupling with the upper level driver for the exchange of messages between the intermediate driver and the upper level driver and a second coupling with the application which controls the exchange of messages between the application and the storage device, and a port driver coupled to the intermediate driver and the storage device.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page.

Abstract: An administrator station for administering and maintaining a plurality of computer network and/or communications servers. A low profile clam-shell display and keyboard apparatus, as utilized in a portable notebook computer, is used to replace a rack mounted cathode ray tube video monitor, keyboard and cursor control devices, and an electromechanical switcher. An interface apparatus translates the video output, keyboard and mouse signals of a plurality of computer servers to a format that may be communicated to the administrator station either through a physical connection or by means of wireless communications such as infrared, cellular or spread spectrum radio. When not in use, the administrator station may be stored in a low profile rack panel located in a rack cabinet having a plurality of computer servers mounted therein. Alternatively, the administrator station may be moved from one rack cabinet of computer servers to another.

Abstract: A system and method for using real mode BIOS calls to load an executable program for execution on a dedicated I/O processor before device drivers which communicate with the I/O processor have been loaded by an operating system. In the preferred embodiment, the system comprises a plurality of x86 processors coupled to a system memory. One of the x86 processors is designated as a dedicated I/O processor. A storage device stores an operating system for execution on the remaining processors, an executable program for executing on the dedicated I/O processor, such as a real-time kernel, and a device driver which is operable to execute on the remaining processors and to communicate with the real-time kernel executing on the I/O processor to perform I/o operations on an I/O device. The storage device also stores a loader program which is loaded by the operating system executing on a first of the remaining processors early in the process of booting the operating system.

Abstract: The invention relates to a computer system having a chassis with an access door allowing a user to access the computer circuitry. The computer circuitry has a plurality of critical circuit boards and an interlock circuit routed through connectors and cables associated with the critical circuitry. If any of the connectors are not connected or connected improperly the main power is prevented from turning on or the main power to the computer is turned off and auxiliary power is used to power indicator lights which aid a user determine which connector is not connected or improperly connected.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A computer system has a computer display with two methods of navigation: discrete and continuous. In discrete navigation, a cursor is moved discretely using a set of arrow keys while in the continuous navigation, a pointer or other screen object has analog movement to any position on the screen using a trackball or other device. When the discrete navigational method is used to highlight a menu item in a menu on a computer display, the computer system masks the display of the pointer until re-activation of the pointer in the second navigational method. In addition, the computer system recalculates the location of the pointer to a position in the center of the highlighted menu item.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page.

Abstract: A method for providing a video buffer includes reserving an incremental video buffer in system memory, and controlling the use of a dedicated video buffer and the incremental video buffer to provide a composite video buffer.

Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.

Abstract: A modular computer chassis for both rack mounting and free standing use comprising a housing adapted for receipt of a plurality of computer modules in a secured array. The modules are selectively accessible only through a cover panel door which may be locked to secure the integrity of the array. The modules are mounted in the chassis on individual slides which afford alignment and stability in the assembly thereof. Additionally, the modularity affords interchangeability with rack-mounted systems for maximizing the efficiency of operation and the effectiveness of installation and service. Problems within the system can thus be addressed by removing and replacing individual modules in a configuration which affords reliability and easy access.

Abstract: Innovative systems and methods for advantageous use of a new isolated power converter topology, in which transformer isolation is provided by a very simple DC-DC converter operated in open-loop mode (with each switch running at a constant duty cycle of approximately 50%, to achieve an effective duty cycle of approximately 100%), and feedback or modulation is instead applied to a preconverter stage which also does power factor corrections. Since the isolation stage is operated at a constant duty cycle, distortion can be minimized and its efficiency can be fully optimized, with a simple circuit and small component count. Unlike a flyback converter, only a very small inductance is required. A simple control architecture is used with current control loop. The disclosed circuit tightly clamps the voltages on the switch and on the transformer, with no ringing nor overshoot.

Abstract: A segmenting scheme and arrangement for digital serial busses such as an I.sup.2 C bus is provided. The segments are broken apart from the master unit by a switch such as a low-impedance bidirectional analog multiplexer. The bus may be of various types such as an I.sup.2 C, a Universal Serial Bus or other similar types of busses. The bus is bidirectional from the various slave or downstream units to the master unit and the various slave devices can operate at different speeds by allowing each segment to adjust the speed of that segment.

Abstract: A method and apparatus of assuring uniqueness of identification numbers of bus devices connected to a bus. Each bus device has a current identification number. At each of the bus devices, an identification number is received on a bus and the bus is contended for based on the received identification number. If more than one bus device is detected contending for the bus, the current identification number of one of the bus devices is changed. Each of the bus devices compares the received identification number to the current identification number of the bus device. A bus device provides a match indication, including driving a signal, if the comparison produces a match. Each bus device includes a collision detector for detecting if more than one bus device is driving the signal.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.