Abstract: A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit successful completion of the transaction. The protocol used depends upon the type of transaction sought by the master device. Once the subtractive agent is identified by address, the bridge keeps track of its location. Thus, further operations targeting the subtractive agent run without requiring either protocol to be used. Further, the need for a specialized signaling protocol to access the subtractive agent is avoided.

Abstract: A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that one partition will undergo pre-charge or refresh in the interim between times in which another partition (or a pair of partitions) initiate a burst read. The burst read cycles coincide with an initial column address of the burst, and are spaced a number of cycles equal to the burst length. Proper spacing of the initial column address, or read request, relative to a non-read requested partition ensures data read from the activated partition will be placed on the memory data bus in seamless fashion. That is, there are no non-data transfers occurring between data burst cycles, even though refresh or pre-charge operations are performed on a non-read partition.

Abstract: An apparatus and method are provided for detecting physical memory connected to a memory slot of a computer. The amount of physical memory within each bank is determined during boot up of the computer. Specifically, an extended physical address range exceeding 232 bytes can be accessed and, therefore, detected from boot up code contained within a ROM. The ROM contains translation tables which allow a 32 bit linear address to be translated to a physical address which can reside at boundary address locations of the fill extended physical address range. Each boundary location can be tested by writing to and reading from the specific boundary addresses to determine if physical memory is present within a sector in which the boundary address page resides. The sectors are equally spaced across the physical address range so that boot up can detect physical memory sequentially along the sector boundaries, either beginning with the lowest addressable sector or beginning at the highest addressable sector.

Abstract: A system for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which in conjunction with the device proxy agent, assigns the memory space assigned to the device proxy agent to hidden devices. A section of memory is allocated as memory address space for the computer bus. A first portion of the allocated memory address space is assigned to non-hidden computing devices and a second portion of the allocated memory address space is assigned to the device proxy agent. The IOP in conjunction with the device proxy agent assigns the memory address space assigned to the device proxy agent to the hidden devices.

Abstract: A modularized computer chassis for housing multiple computer modules, such as a processor module, media storage module, an I/O module, and power supplies includes a housing divided generally into four regions, with each region configured for receiving one of the modules or power supplies. A single center pluggable midplane board is positioned in the middle of the housing such that each of the modules and power supplies can be interconnected through the single midplane board. The single center pluggable midplane board includes direct pluggable connectors which correspond to connectors on each of the modules and power supplies, such that each of the modules and power supplies are directly connected to the single pluggable midplane board, and no ribbon signal and power cables are needed for the connection. The direct connection between the single center pluggable midplane board and the modules and power supplies helps to minimize the height of the chassis, thereby saving valuable rack space.

Abstract: An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus.

Abstract: A SCSI bus extender apparatus coupling a main SCSI bus to a auxiliary SCSI bus includes a mechanism for detecting and processing SELECTION and RESELECTION signals transmitted between the two buses to accommodate target devices on the auxiliary bus which support tagged queuing in accordance with the SCSI protocol. The invention contemplates reserving an address on the auxiliary bus for each initiator on the main bus and performing the appropriate address conversions to enable target devices to properly identify the correct initiator device during a RESELECTION phase.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: The present invention provides an improved home location register (HLR) that includes an application program for implementing configurable call forwarding bins in a mobile telephone system. According to the invention, a number of call forwarding bins are provided for subscribers. Each forwarding bin must be individually authorized to become available to a subscriber. Furthermore, if a bin is authorized, depending on whether a bin is locked or not, either the cellular carrier or the subscriber can activate the bin and/or modify a forward-to number in the bin. Moreover, a priority list is provided, corresponding to a particular status of the subscriber's cellular phone. (i.e. busy, no answer, etc.) and whether the subscriber is in the home area or a roaming area. The priority list identifies selected bin numbers that the application program needs to check. The bin that has the highest priority on the list and is authorized and activated will be selected.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A digital system that includes a main printed circuit board that has a first conductive portion formed thereon is provided. A microprocessor module is coupled to and extends orthogonally from the first conductive portion of the main circuit board. A voltage regulator printed circuit board is coupled to and extends orthogonally from the first conductive portion of the main circuit board adjacent the microprocessor module. The voltage regulator printed circuit board supplies a regulated voltage to the microprocessor module over the first conductive portion.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare.

Abstract: A memory storage system includes a motherboard, a first memory card, and second memory card. The motherboard has a first and second electrical connector. The first memory card has a plurality of electrical connections coupled to the first electrical connector on the motherboard. The first memory card is adapted to receive a plurality of data signals over the first electrical connector and store the data signals in a first preselected pattern. A second memory card has a plurality of electrical connections coupled to the second electrical connector on the motherboard. The second memory card is adapted to receive a plurality of data signals over the second electrical connector and store the data signals in a second preselected pattern, different from the first preselected pattern.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.

Abstract: A planar-type magnetic structure in which two coils, on two poles of the same core, are separated by an open space which is wide enough and low enough that the air return flux, through the open space, completes the flux circuit for each coil. Thus the coupling coefficient between the two coils is very small, even though they are both mounted on a single continuous core of high-permeability material.

Abstract: An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.