Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.

Abstract: A graphics processor uses a line draw facility to receive first and second values indicative of the coordinates of respective first and second end points of a line. The reception of the second value is sensed by the line draw facility and line data is generated responsive to the sensing of the second value.

Abstract: A solid state safety relay comprises: a first driver circuit; a second driver circuit; a charge disconnect transistor coupled to the first driver circuit and configured to control the flow of current along a current path; a first discharge disconnect transistor coupled to the first driver circuit and configured to control the flow of current along the current path; and a second discharge disconnect transistor coupled to the second driver circuit and configured to control the flow of current along the current path. A method of isolating an energy source from a circuit current path, comprises: turning off a first discharge disconnect transistor coupled to the circuit current path; and turning off a second discharge disconnect transistor coupled to the circuit current path to permit isolation of the energy source from the circuit current path if either one of the first discharge disconnect transistor or the second discharge disconnect transistor fails.

Abstract: Iterative information retrieval from a large database of textual or text-containing documents is facilitated by automatic construction of faceted representations. Facets are chosen heuristically based on lexical dispersion, a measure of the number of different words with which a particular search expression co-occurs within a given type of lexical construct (e.g., a noun phrase) appearing in the document set. Words having high dispersion rates represent “facets” that may be used to organize the documents conceptually in accordance with the search expression, effectively providing a concise, structured summary of the contents of a result set as well as presenting a set of candidate terms for query reformulation.

Abstract: An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K, wherein K is the smallest integer such that the difference between any two adjacent bytes is expressible in K bits or less, outputs an indication of K and outputs a K bit difference between the byte and an immediately prior byte, for each byte in the set.

Abstract: A display system for concurrently displaying stored display information and received information, having a display monitor, receiver for receiving television signals, and a sub-system having a storage unit and a processor, which sub-system can operate simultaneously with the receiver. The stored display information comprises application information portion and sponsor information portion which may be downloaded via a vertical blanking interval or a portion of the bandwidth associated with digital signals.

Abstract: A cordless modem system where a mobile station unit (MSU) is located in the computer and a base station unit (BSU) is connected to the telephone line. A radio frequency (RF) link is developed between the two units to allow a cordless connection. A series of commands are used between the two units to allow the MSU to request a channel, the BSU to grant a channel, the BSU to notify of a ring, and the MSU to request the BSU to go off hook. In addition, there is preferably a command sequence to allow authorization of a particular MSU or BSU. There are two full duplex channels in each MSU and BSU. This allows multiple BSUs and MSUs to be utilized in a small area. Communications between the two units are secure based on address values for each unit contained in the various commands. The communications software utilized in the computer is not even aware of the presence of the cordless connection.

Abstract: A file placement process operates to respond to requests for creation of a file, accompanied by file statistics, such as storage space needed by the file, to locate a storage volume having space best fitting the file statistics.

Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.

Abstract: An efficient solution to transform an output from a single ended source to a pair of differential signals that are provided to a differential receiver. The differential receiver is any number of devices including a differential clock receiver. The differential signals may be referenced to voltages used to receiver power supply voltages. The present invention obviates the need for an additional differential driver and its required additional devices that are needed to perform transformation of a single ended signal to a pair of differential signals. In one embodiment, two independent power and ground planes are communicatively coupled via a transmission line, or transmission line-like traces on a printed circuit board, and are used to provide uniform impedance control for all return paths within a system.

Abstract: An audio system for multimedia computer systems and method for use are provided including an audio module having speakers, a microphone and associated circuitry. The audio module is adapted to be interposed between a monitor and a monitor pedestal such that the audio module swivels and tilts in concert with the monitor. The circuitry is adapted to drive the audio module speakers and to drive only one speaker and the microphone in a speaker phone mode.

Abstract: A protective assembly for electronic components. The protective assembly has a base and a first printed circuit board secured to the base. An electronic component is disposed on the printed circuit board and protected by a rigid member that is also secured to the base. The protective assembly is designed to be mechanically and electrically coupleable to a computer-based system.

Abstract: An invention is disclosed for providing a signal indicating whether a processor is installed and providing improved voltage regulation. A contact is selected and isolated from an array of ground contacts and is further coupled with circuit for generating an INSTALL signal. A capacitor and pull up resistor coupled to a supply voltage, ground and the isolated contact form a signal line at a common node such that a circuit to ground is completed through the processor and the isolated contact when the processor is plugged in and a direct signal indication of the presence or absence of the processor is provided. Voltage sense lines of a Voltage Regulation Module (VRM) are coupled directly to processor contacts isolated from an existing voltage supply contacts coupled to the supply plane of a supply voltage within the circuit board providing improved regulation without adversely affecting power supply current capacity considerations.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: Systems and Methods for identifying in the gateway processes or application processes whether an imported transaction is a loop-back transaction, and if so performing work for the imported transaction under the parent transaction. Upon receiving a work request from a remote transaction processing system, an endpoint identifier included as part of the work request is analyzed to determine whether the work request is associated with a parent transaction initiated at the local transaction processing system. If the endpoint identifier indicates that the work request is associated with a transaction initiated in the local transaction processing system, a global transaction identifier included as part of the work request is analyzed to determine the identity of the parent transaction. If the work request includes a remote TIP URL, the application process that receives the request is configured to analyze the global transaction identifier and determine the identity of the parent transaction.

Abstract: A method and apparatus for logging errors in a storage device. As commands are executed by the storage device a list of previously executed commands is maintained. When an error is detected by the storage device, the previously executed commands and certain error condition codes are stored in an error log in a non-volatile memory of the storage device. The storage device is responsive to a command for reading back the values contained in the error log for diagnostic purposes.

Abstract: An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of performance enhancing and degrading events regarding a cache are counted and compared to a threshold. When the threshold is triggered the cache becomes a candidate for purging. In an embodiment, a time out delay is implemented before actual purging occurs. When the threshold is not triggered but a cache event occurs, a fake time out delay is triggered and the count is adaptively either raised, lowered or set to zero in response to performance enhancing and/or degrading events. The effect is to make the actual purging more likely if the history of cache events indicates that the performance would be enhanced thereby or less likely if the history indicates that the performance would be degraded thereby.

Abstract: A system for seamless distributed job control between a multifunction peripheral and a host. A host, such as a personal computer, is linked with one or more multifunction peripherals. Each multifunction peripheral has at least scanning and printing capability. However, the peripherals do not require extensive memory or processing capability, because the processing and storage of data is accomplished by the host. A user potentially may operate the peripheral through a peripheral interface or through a user interface of the host.

Abstract: A peripheral control interface provides access to a system area network for a plurality of peripheral devices connected to the PCI through an I/O bus. A plurality of virtual data channels is defined in local memory to which outstanding requests from peripherals are assigned. Physical channel engines implement the order requests through the assigned virtual data channel with accessed data stored in local memory. A subsequent request by a peripheral can then be immediately fulfilled from data stored in memory. Data channel context stored in memory includes the number of outstanding requests by a user to whom the channel is dedicated, and a physical channel engine can pre-fetch data in response to a plurality of outstanding requests from a peripheral thereby eliminating latency in fulfilling requests.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g.