Abstract: A multiple segment network device configured for a stacked arrangement via a common backplane. The device is a repeater that includes a first repeater segment, a second repeater segment and a switch device disposed between the first and second repeater segments that enables communication therebetween within a single logical network domain. The device further includes a backplane connector coupled to the second repeater segment to enable extension of the second repeater segment to a common backplane with external devices while maintaining a single repeater domain. The first repeater segment operates at a first transmission rate and the second repeater segment operates at a second transmission rate. The switch device may be a learning bridge that filters information between the first and second repeater segments. The common backplane enables two or more repeaters to be coupled within the same logical network domain or LAN.

Abstract: A input device, such as a keyboard, having an array of unique rapid response keys for responding rapidly and conveniently to routine requests from software applications. Such routine requests include those requiring a “yes,” “no” or “cancel” response. Other routine tasks includes saving and closing files, which typically causes software to issue a save request. Instead of responding to such requests with input from a pointing device, the unique rapid response keys allow a user to respond to such routine requests without removing her hands from the keyboard. Four dedicated keys are preferably located above an escape key on the keyboard. A device driver receives scan codes from the keyboard and translates the scan codes corresponding to the response keys for providing a properly formatted response to the requesting software application.

Abstract: Method and apparatus is provided for securely configuring a programmable hardware device from a remote source. The programmable hardware device includes a plurality of programmable logic modules. A host receives configuration information from the remote source, where the configuration information defines a function of the programmable logic modules. The host encrypts the configuration information according to a cryptographic algorithm. The encrypted information is transferred to a special download engine at the programmable hardware device, which decrypts the information according to the same cryptographic algorithm. The programmable logic modules are thus configured by the decrypted configuration information, which has been securely downloaded from the remote source.

Abstract: A computer system having electronic components housed in a central unit having a protective enclosure and a cover. The cover is moveable to provide access to electronic components housed in the central unit. The cover allows access to certain electronic components and prevents access to other electronic components.

Abstract: A regulated power supply in which square wave output of a switching rectifier is applied to a filter comprises a series inductor and a parallel capacitor. This filter lacks a series resistor. The ramp signal is developed across a second capacitor in series with a first resistor, and in parallel with the rectifier output. An amplifier adds the ramp signal to a signal representing the error in the DC output voltage of the power supply, producing an output that is fed to a control circuit. The control circuit in response generates a voltage control signal that controls the switching of the rectifier.

Abstract: In a computer system two integrated circuit devices are operatively mounted on the main system board using a pair of interstitial circuit boards sandwiched between the integrated circuit devices and the system board and having substantially smaller footprints than the system board. Each interstitial board has a series of terminating components, representatively resistors, interposed in its circuitry which interconnects the associated integrated circuit board with system board circuitry that, in turn, operatively couples the two integrated circuit boards. The incorporation of the terminating components in the interstitial boards instead of in the system board reduces the circuit complexity of the system board and the required number of layers therein, thereby reducing the cost of the system board and substantially simplifying its signal trace routing design.

Abstract: An electronic commerce system and method enforces a license agreement for content on an open network by restricting the number of consumers that can concurrently access the content. A consumer initially acquires vendor scrip, either from a broker or the vendor itself. The consumer presents the vendor scrip to the vendor along with a request to access the content. In response, the vendor gathers information about the consumer to determine whether the consumer belongs to the class allowed to access the content. The information may be gathered from the scrip or from other sources. If the consumer belongs to the class, then the vendor determines if a license to access the content is available. Generally, a license is available if the number of other consumers having licenses to access the content is less than the maximum specified in the license agreement. If no licenses are available, the vendor provides the consumer with an estimate of when a license will be available.

Abstract: A system, method and computer program product for hardware assisted backup for a computer mass storage subsystem wherein files to be backed up from a source storage medium (e.g. disk) to a formatted storage medium (e.g. tape) are written in logical block number (“LBN”) order regardless of the file's on-disk layout. If the source file structure information is available it is used or the disk blocks containing the file structure are marked in a used (or “free”) block bit map which may then be modified to exclude files that are “open for write”, marked as “no backup” or not part of the selected file save operation. In operation, the blocks are written to tape using a Tape Copy Data (“TCD”) command. Blocks that were selected, but excluded as “open for write” may then be written to the tape utilizing more conventional methodologies.

Abstract: In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sections to one another, thereby allowing groups of the processor units to be physically spaced from one another. The fiber optic interconnect system includes, for each multiprocessor unit section functions to receive messages communicated on the interprocessor bus of that section for receipt by a destination processor of the other section, format the message for fiber optic transmission, and transmit the message; and circuitry for receiving messages on the fiber optic link, scheduling the message for transmission to the destination processor, and maintaining that scheduling in the face of receipt of another message for the same processor unit.

Abstract: In a multiple processing system or cluster, a pair of processes, assuming the role of a primary process and a backup process to the primary process, are replaced on-line by stopping the backup process; creating the replacement backup process; checking to ensure compatibility between the primary and replacement backup processes so that communication between them is possible and information sent by the primary process to the replacement will be correctly received and handled; providing the replacement backup process with that state of the primary process needed in order to take over the function and operation of the primary process; switching roles so that the replacement backup process now takes over the function and operation of the primary, and the primary becomes the backup; and repeating the steps of creating, checking, providing and switching, to conclude with a newly-installed replacement primary process and a replacement backup process, completing the on-line replacement of the process pair.

Abstract: A computer system with various component modules with each of the modules interconnected with a single midplane board, thereby eliminating the need for ribbon cables to interconnect between the modules. One of the modules includes an embedded controller and associated data bus. An in-line connector is coupled in the data bus which receives either a jumper connector or interconnect connector. The interconnect connector intercepts the data bus from the embedded controller and transfers connection to a user added controller. The interconnect connector can operate in two modes, a single mode and a differential mode. The interconnect connector includes logic circuitry that determines the type of controller connected and places the interconnect connector in the appropriate mode. If the logic circuitry detects that a single-ended controller is connected to the interconnect connector, a quick switch, which is connected to one wire of the data bus, is closed, thereby grounding the one wire.

Abstract: A language translator is provided which determines memory structure at compile time for a plurality of object classes including at least one virtual base class and at least one class derived therefrom. At compile time, space for pointers (b-pointers) is set aside in each class object that will have a base table (b-table) associated therewith. The b-pointers point, at run time, to an associated b-table containing memory offsets between the base classes of the derived class. At run time, constructors construct the class objects, starting from the most derived class object and proceeding through to the base class object. However, instead of generating the virtual tables and associated pointers, as well as the adjusting functions, at compile time, the language translator generates the code for these operation to be executed at run time. Then at run time, a virtual function table is generated for the base class.

Abstract: A cabinet system includes first and second cabinets each including first and second side walls, upper and lower rectilinear frames extending between the side walls at vertically spaced-apart locations therealong and weldments connecting the upper and lower frames to the side walls to form a rigid housing. A pair of spaced-apart locating holes are formed in the side wall of the first cabinet adjacent to the lower frame thereof and an additional locating hole is present in the first wall of the first cabinet adjacent to the upper frame thereof. Further, a pair of spaced-part locating pins are provided in the second side wall of the second cabinet adjacent to the lower frame thereof along with an additional locating pin in the side wall of the second cabinet adjacent to the upper frame thereof.

Abstract: A method schedules execution contexts in a computer system based on memory interactions. The computer system includes a processor and a hierarchical memory arranged in a plurality of levels. Memory transactions are randomly sampled for a plurality of contexts. The contexts can be threads, processes, or hardware contexts. Resource interactions of the plurality of contexts is estimated, and particular contexts are chosen to be scheduled based on the estimated resource interactions.

Abstract: A method and apparatus for discovering, identifying and graphically representing network devices on a network. The devices are discovered by obtaining the gateway address of the management workstations and then reading the internet protocol address table and the ARP cache from each gateway via SNMP. Each address read is compared with existing IP addresses, and if new, device IDs are created and assigned. Select attributes are then assigned to each device and then the devices are then identified. The devices are identified by making a DNS request on the corresponding IP address to determine the network name of the device. The SNMP then obtains the system name and object ID (OID) for each of the devices. The OID is then compared and matched with known OIDs to identify the device. the devices are graphically connected and laid out by creating a submap based on the IP address and mask pairs for each device. The routers connected, the bridges are then connected and finally the repeaters are connected.

Abstract: A customer information control system (CICS) application programming interface (API), with transient data queue functions, in a loosely coupled data processing environment. In accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed to a method, system and computer readable medium including program instructions (hereafter collectively referred to as the “invention”). In particular, the invention includes implementing a loosely coupled CICS region in a data processing environment, the loosely coupled CICS region including at least two of a plurality of address spaces each of which being associated with a machine. The invention further includes providing at least one CICS-API operating system server (COSS) within the loosely coupled CICS region, each COSS operating in one of the at least two address spaces within the loosely coupled CICS region.

Abstract: A hot-pluggable disk drive is supported on a carrier structure that is slidably and removably insertable rearwardly into a sheet metal cage portion of a computer system to releasably couple an SCA connector on the rear end of the drive to a corresponding electrical connector on a backplane structure within a rear interior portion of the cage. The carrier structure includes a base wall upon which the disk drive rests, and a pair of transverse side walls disposed on opposite side edge portions of the base wall. To substantially reduce self-induced, performance degrading operational vibration of the inserted drive about the rotational axis of its platter section, outward projections are formed on the opposite side wall portions of the carrier in a forwardly offset relationship with the rotational axis of the drive. As the drive is inserted into the cage, these projections slidingly engage and form an interference fit with inwardly bent opposing side wall portions of the cage.

Abstract: A notebook computer has a keyboard including a deflectable base plate on the top side of which a series of parallel rows of depressible key structures are operatively mounted. The base plate is structurally reinforced, without increasing the overall height of the keyboard, using elongated stiffening ribs disposed within the interior of the keyboard. The ribs longitudinally extend parallel to the key rows, are anchored beam-like to the top side of the base plate, and are interdigitated with the key rows.

Abstract: A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.