Abstract: A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A PCI-based computer system is provided with an expanded number of PCI master devices, in effect a second level of PCI arbitration. The expansion is made available without requiring additional bridge chips. Multiple PCI devices may arbitrate for control of the PCI bus via the primary PCI bus controller without requiring a specifically assigned signal pair, yet appear to system software to reside on the primary PCI bus.

Abstract: A computer password security method employing a south bridge circuitry where the user password is compared to a secured password stored in secured memory which is directly accessible to the south bridge circuitry, removing any threat of data bus and/or unprotected memory snooping.

Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i.e., target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order.

Abstract: A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI/power management logic capable of supporting a Device Idle mode in which selected I/O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI/power management includes status registers that are used to determine when a device in low power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry signal.

Abstract: A video teleconferencing method and apparatus for computer workstations connected by a digital data network includes a transmission source means for a local workstation to send audio and video teleconference data across the network to one or more remote workstations, and, a receiver for the local workstation to receive audio and video teleconference data back from the remote workstations. The local workstation sends teleconference data to each of the remote workstations over a variable bandwidth digital data connection, and each of the remote workstations returns teleconference data back to the local workstation over another variable bandwidth digital data connection. The transmission source means includes a master software process executing on the local workstation, and the receiver includes a slave software process executing the remote workstation.

Abstract: An encoded loss resilient message, includes a first number of first data items, a second number of second data items, and a third number of third data items. Respective portions of the first data items correspond to different numbers of associated second data items in a first distribution. Respective portions of the second data items correspond to different numbers of associated first data items in a second distribution. Respective portions of the second data items correspond to different numbers of associated third data items in a third distribution which is proportional to the first distribution with the different numbers of associated third data items equaling the different numbers of associated second data items multiplied by the first number divided by the second number.

Abstract: The present invention provides integrated packaging for storing or transporting a circuit assembly. In an embodiment of the invention, a housing comprises a first side portion attached to the circuit assembly, a second side portion and means for coupling the first side portion to the second side portion wherein the second side portion is moveable to a first position when the circuit assembly is operating and the second side portion is moveable to a second position when the circuit assembly is to be transported, so that the housing encloses the circuit assembly.

Abstract: A computerized method selectively accepts access requests from a client computer connected to a server computer by a network. The server computer receives an access request from the client computer. In response, the server computer generates a predetermined number of random characters. The random characters are used to form a string in the server computer. The string is randomly modified either visually or audibly to form a riddle. The original string becomes the correct answer to the riddle. The server computer renders the riddle on an output device of the client computer. In response, the client computer sends an answer to the server. Hopefully, the answer is a user's guess for the correct answer. The server determines if the guess is the correct answer, and if so, the access request is accepted.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latency, and state information of the system is sampled while any of the selected instructions are in any stage of the pipeline. Software is informed whenever any of the selected instructions leaves the pipeline to read the event and latency information.

Abstract: A computer system incorporating capabilities for displaying the audio disk track number when the computer system is playing an audio disk. The computer system determines if a disk is present in the disk drive. If a disk is present, the computer system determines if an audio disk is present in the disk drive. If so, the computer system then monitors the disk drive. When the audio disk is played by the disk drive, the computer system displays the audio disk track number. The computer system then periodically polls the disk drive to update the audio disk track number. The computer system displays a battery gauge status when the audio disk track number is not being displayed. The status display is visible when the portable computer is in either an open or closed state.

Abstract: A method and apparatus for controlling acoustic gain during a non-speakerphone audio mode of computer system independent of acoustic gain during a speakerphone mode of the computer system is provided. The BIOS code of the computer system detects whether the computer system is in a speakerphone mode or a non-speakerphone audio mode. If the computer system is in a speakerphone mode, an upper gain limit is not applied to the microphone path of the computer system. If the computer system is in a non-speakerphone audio mode, a predetermined upper gain limit is applied to the microphone path of the computer system. The predetermined upper gain limit is preferably applied to the microphone path at either a microphone pre-amplifier or an audio mixer chip in the microphone path of the computer system.

Abstract: A portable computer docking base has incorporated therein a thermoelectric cooling system used to provide auxiliary operating heat dissipation for a portable notebook computer operatively docked to the base. The cooling system includes a thermoelectric (Peltier effect) heat pump unit disposed within the docking base housing and having opposite hot and cold sides. A finned heat sink member is secured to the hot side of the assembly and positioned in the path of fan-generated cooling air, and a heat slug member is secured to the cold side of the assembly and projects outwardly through an exterior wall of the docking base housing into its computer receiving area. When the computer is placed in the receiving area and docked, the is cooling system heat slug member is brought into heat conductive contact with a similar heat slug member carried within the computer and thermally coupled to its microprocessor.

Abstract: A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

Abstract: A resettable memory apparatus includes a random access memory including a plurality of memory locations, each memory location stores a plurality of bits of data. A single register has a plurality of bits, there is one bit for each of the plurality of memory locations. A reset signal resets all of the bits in the register to invalid. A reset value is generated when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory. Writing data to the particular memory location sets the corresponding bit in the register to valid. Subsequent reads to the location while produced the data stored therein as long as the corresponding bit in the register remains valid.

Abstract: A computer system is implemented according to the invention when an computer process allows a user to determine a desired computer configuration by in part determining performance relative to price candidate configurations.

Abstract: A new system for communicating between computer programs is disclosed which includes a collaboration software program having a directory publishing procedure and a message forwarding procedure. In an example embodiment, the disclosed system provides a user of a network application program, such as an internet chat program, with an out-of-band mechanism to send invitations to other users of the network application program. A user of the network application program requests a list of all users known to the collaboration software program. The user list is for example a list of user names associated by the collaboration software program with URLs of home pages of users known to or registered with the collaboration software program. The user seeking to send the message then selects a user name and provides a message to the collaboration software program. The collaboration software program then posts the message so that the message can be displayed in the home page of the selected user.