Abstract: A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

Abstract: A computer system is implemented according to the invention when an computer process allows a user to determine a desired computer configuration by in part determining performance relative to price candidate configurations.

Abstract: Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data inconsistency among multiple devices associated with a shadow set for storing data. The disclosed system includes techniques for allowing continued data accesses while simultaneously re-establishing data consistency among members of the shadow set.

Abstract: A resettable memory apparatus includes a random access memory including a plurality of memory locations, each memory location stores a plurality of bits of data. A single register has a plurality of bits, there is one bit for each of the plurality of memory locations. A reset signal resets all of the bits in the register to invalid. A reset value is generated when reading a particular one of the memory locations while the corresponding bit in the register is invalid to provide a resettable random access memory. Writing data to the particular memory location sets the corresponding bit in the register to valid. Subsequent reads to the location while produced the data stored therein as long as the corresponding bit in the register remains valid.

Abstract: A prediction mechanism is provided for determining a bank of a secondary cache and a tag sub-store corresponding to a data element requested by a central processing unit. The mechanism employs a bit number select logic for determining unique bit number locations of differences between selected tag sub-store values. Those unique bit number locations are based upon the values of the tag sub-stores at previously determined difference locations. The bit number locations, and the values of the tag sub-stores at those bit number locations, are stored in a distinguishing bit RAM. When a main memory access is initiated, the values of the tag sub-stores at those bit number locations are compared with corresponding values of the tag portion of the main memory address. When that comparison indicates that selected ones of the tag sub-store values are equivalent to the corresponding values of the tag portion of the main memory address, an associated bank of the secondary cache is accessed.

Abstract: A system and method for automatically mapping on a computer display a graphical representation of a physical arrangement of a plurality of computer components in one or more cabinets, each cabinet having one or more shelves for housing the computer components. The status of the components is periodically monitored and the computer display updated accordingly. A graphical user interface is provided for user observation of the physical arrangement and status of computer components in the cabinets, as well as user control of the operational parameters of the components.

Abstract: The present invention makes it possible to safely hot plug a PCI expansion slot connected to a 64 bit, 66 Megahertz PCI bus. The PCI bus comprises a plurality of signal lines connecting a PCI Controller to the expansion slot. On each signal line there is a quick switch disposed thereon to detach the signal line from the expansion slot. A bus_enable signal activates the quick switches and a Req_64 mode line to detach or attach the PCI bus from the expansion slot. The Req_64 mode line bypasses the quick switches and goes through a crossbar switch. The crossbar switch has its open state set to an active low wherein the 64 bus mode is thereby communicated to the card as an active low even when the other signal lines of the bus are in a high disconnected state.

Abstract: A method and apparatus provide a mechanism for a personal computer to allow the insertion and removal of devices to and from device ports without re-starting the operating system of the computer. Device drivers are pre-loaded during the start-up process of the computer system for devices that may be inserted in the system later. Upon detection of device insertion, a high priority thread process determines the type of device inserted and determines which pre-loaded device driver can operate the newly inserted device. The selected device driver is linked to the file system and is activated by signaling to the device driver or to the operating system of the existence of the newly inserted device. The operating system can then operate the inserted device. Upon device removal, device drivers for the removed device can be deactivated. The system also allows a docking station to have devices added or removed from device ports after the docking process has been completed.

Abstract: A shared persistent memory (e.g., disk) file system provides persistent memory block allocation with multiple redo logging of memory blocks. The file system employs a three part block state indicator (V,A,U). V is a volume indication. A is allocation sequence indication. U is update sequence number indication. The file system (a) generates indication of the allocation sequence in the allocation map in a manner free of initially reading the block from storage memory, (b) records the indication of volume, allocation sequence and update sequence in an entry of the transaction log of the requesting computer node, and (c) sets indications of volume, allocation sequence and update sequence on the subject block in storage memory. Subsequent transactions on the subject block, by the requesting node are recorded in respective entries in the transaction log. Each respective entry reflects state of the subject block by indicating in the block state indicator the volume, allocation sequence and order of update sequence.

Abstract: A method of reconstructing an image from a dithered image. A predefined set of filters having different regions of support is established. Each filter is defined by a number of filter coefficients and an impulse response function which defines the filter response for a region of support outside of which the impulse response is zero. Filters are organized according to indexes and this organization represents the order in which the filters are considered during a filter selection process. The filter selection process selects a filter constrained by the rule that the filter selected must only perform low-pass filtering on a region of support that does not contain edges of an image. Due to the organization of the filter set, the filter selection process first selects the largest filter from the filter set that fits within the region about the current processed pixel. If there is an edge of an image within the support region of the first selected filter, the next smaller filter is selected.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, with entry points for calls to replace input/output instructions. In this way, standard device driver code written to execute input/output operations is easily converted to operate with the “virtualized” UART.

Abstract: An apparatus includes a cabinet, a keyboard assembly, and a switchbox. The cabinet has mounting rails. The keyboard assembly includes a keyboard tray and a keyboard slide. The keyboard slide has fixed and moveable portions. The fixed portion is mounted to the mounting rails, and the moveable portion is mounted to the keyboard tray. A switchbox is mounted to the fixed portion of the keyboard slide.

Abstract: A specially designed stand structure is used to vertically support a docking station housing, and an associated portable computer removably coupled thereto, to substantially reduce the vertical footprint of the overall docking station system. The stand structure includes a base portion having a recessed area for receiving and supporting a section of the docking station housing, and a pivotally mounted vertical holding wall structure with a transverse lower receiving platform. The vertical holding wall structure is spaced apart from and faces a vertical guide surface of the docking station housing, with the platform extending toward the guide surface.

Abstract: A phantom-resource memory address mapping system reduces access latency in a memory configured as a stacked-hybrid or filly-interleaved hierarchy of memory resources. The address mapping system comprises memory access circuitry having a topology that combines an interleaved-based translation function in parallel with a stacked-based translation operation. The translation functions operate in conjunction with a phantom-resource memory mapping technique. The memory address mapping system reduces the latency incurred when accessing data in response to a memory reference address, while allowing flexibility with respect to the sizes and amounts of memory resources (e.g., modules, arrays and banks) that may be populated in a data processing system.

Abstract: A portable computer system incorporating a rear projection display. The rear projection display is housed in a display enclosure that is movable between an open and closed position, and incorporates either a pliable or deformable projection surface or a projection surface formed of multiple rigid components. When the display enclosure is open, the projection surface is configured to expand beyond the form factor dimensions of the base portion of the portable computer. In the preferred embodiment of the invention, the projection surface is a pliable material that can be safely deformed or collapsed within the display enclosure when it is closed. The rear projection display thereby allows the effective viewing area of a portable computer display to be increased without negatively impacting the form factor dimensions or weight of the portable computer.

Abstract: A technique for updating a background image is disclosed. In one embodiment, the technique is realized by obtaining at least two representations of an image. At least one portion of at least one of the at least two representations is identified. An updated representation of the image is then provided by averaging together the at least two representations excepting each identified portion.

Abstract: A fingerprint authentication methodology in which a smart card with a credit card form factor is used to transmit the imprint of a fingerprint to a live-scan device. Use of a credit card form avoids direct contact of the imprint with the live-scan device, reducing wear and tear on the live-scan device. Use of a “smart” card to store an imprint template enables the owner of user to maintain control of the print.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a novel manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: An alarm monitoring apparatus and method allows a user of a management station to dynamically create and flexibly configure SNMP traps based on any management information base variable without having to define an exhaustive set of trap definitions in a management information base. Apparatus for monitoring status of a network device includes a processor assembly coupled to the network device and a data memory member accessible by the processor assembly for indicating user-defined alarm thresholds of the subject device. The processor assembly obtains threshold data from the data memory member and compares current status to the obtained threshold data. Upon a threshold being met by the current status, the processor assembly transmits an indication of threshold condition of the subject device to a system management station across a network. The data memory member is a database formed of a plurality of records defined by a management information base.

Abstract: A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked loop (PLL) is provided to establish multiple phases of a first reference clock. One of those phases is selected as a second reference clock, and a second PLL synchronizes the clocking signal to that second reference clock. Each subsystem and associated load which receives the clocking signal has a corresponding clock generation circuit comprising the second PLL. The second PLL for one subsystem can adjust the clocking signal phase prior to that subsystem receiving the clocking signal. The amount by which the second PLL adjusts phase on clocking signal may be different than that by which another, second PLL adjusts the clocking signal arriving on another subsystem.