Abstract: In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Abstract: A disaster tolerant computer system for protection of electronic databases is achieved by cascading storage controllers to accomplish local and remote disk shadowing. A host computer is connected to a local superordinate storage controller via a local data bus. The superordinate storage controller transmits data via a long haul data link to a remote subordinate storage controller. Additionally, the superordinate controller transmits data to a local subordinate storage controller via a local data bus. Consequently, in-band storage capacity is provided remotely, as well as locally, to increase data storage capacity for database shadowing. Furthermore, the cascading of controllers may be used to increase the effective storage capacity of the computer system by using the increased storage capacity for the writing of non-redundant data.

Abstract: A method and apparatus for selectively incrementing a count number associated with a node which is subject to a compare and swap operation in a concurrent non-blocking queue. A memory stores data in a plurality of nodes residing in at least one queue. The plurality of nodes store both data and references to other nodes within the queue. An address of each node includes a pointer and a count number. A plurality of processors access the memory and operate on the plurality of nodes including performing a compare and swap operation. The count number of a node is selectively incremented only upon a successful compare and swap operation when the node is put in use by removing the node from an available source of free nodes and placing the node on the queue. Otherwise, the count number of the node is preserved.

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of registered peripheral component interconnect (“PCI-X”) buses capable of operating at 66 MHz. Each of the plurality of PCI-X buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI-X device connected to the plurality of PCI-X physical buses. Each of the plurality of PCI-X buses has its own read and write queues to provide transaction concurrency of PCI-X devices on different ones of the plurality of PCI-X buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI-X device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses.

Abstract: A display system having a computer, a video source, a graphics refresher and a display monitor, the display system comprising a first buffer for receiving a first portion of video data from the video source; a second buffer for receiving a second portion of video data from the video source; and a third buffer for receiving a third portion of video data from the video source, wherein the graphics refresher generates signals for selectively displaying one of the portions of the video data on the display monitor.

Abstract: A stereo speaker system for portable computers which maximizes spatial impression by using rearward-firing speakers, mounted in the back of the display, in combination with forward-firing speakers mounted on the chassis or in the front side of the display.

Abstract: An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of a predetermined number (N) of clock cycles. The total number of instructions processed over the last P clock cycles is computed, where P is less than or equal to N. The total number of instructions processed is divided by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle. This average number of instructions processed is communicated to software.

Abstract: An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template including an M by N matrix of integer threshold values, the uniform distribution of threshold values throughout the dither template possessing homogeneous attributes. The apparatus further includes a normalizer unit for normalizing the threshold values of the dither template for storage in a dither matrix according to the first plurality of chrominance or luminance levels of the input image pixels and a second plurality of chrominance or luminance levels of the output array and a summation unit to add the input image pixel chrominance or luminance values to the normalized threshold values of the dither matrix.

Abstract: A integrated content guide for multiple sources is provided with hyper-text type links to allow for the selection of various programs. The hyper-text links are provided for a transmitted and then stored digital bit stream. This allows for the embedding within the content guide what could be additional commercial information. The embedding may also be as to additional information for other related television or radio shows or the like. Information can be additional television shows, related information or activities on on-line services or automatic telephone ordering of products or services being displayed.

Abstract: A method and apparatus for allowing an Authentication Center (AC) to configure whether or not to perform automated A-key updating for a handset if an authentication failure occurs during an operation attempted by the handset. The AC has access to a Subscriber database describing, among other things, an “alternate A-key” for at least some of the subscribers. The AC also has access to database that contains configuration information about various MSCs in the system.

Abstract: A method of producing, on a physical medium, a gradient tonal representation of an image and a printhead for producing the same. An input image is divided into first and second regions. First, continuously variable intensity level, continuous tone and second, discretely variable intensity level, half-tone portions of the representation which respectively correspond to the first and second regions of the image are then printed by depositing selected quantities of ink on the first and second portions of the physical medium such that each pixel thereof has an ink intensity level corresponding to the image intensity level for the corresponding one of the pixels of the first region of the image.

Abstract: A method and apparatus for selectively incrementing a count number associated with nodes which are subject to a compare and swap operation in a concurrent non-blocking priority queue. A memory is partitioned into a free list and a priority queue, and stores data in multiple nodes residing at least in the free list. Each node has a pointer and a count number associated therewith. Multiple processors access the memory and perform a compare and swap operation on the nodes. The count numbers associated with nodes are next fields selectively incremented only upon a successful compare and swap operation of a node being enqued behind it and when the enqued node is put onto one of the lists of the priority list.

Abstract: A computer system with an Intelligent Input/Output architecture having a plug-and-play control mechanism for assigning and controlling one or more adapters. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices or adapters operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. Initially, a selected adapter is defaulted to an “assigned” state without changing the interrupt routing associated with the adapter. Upon detecting the presence of a driver module that is executable on the IOP, the assigned adapter is marked as “controlled” and the interrupt routing is configured to deliver interrupts to the IOP. Subsequently, the controlled adapter is rendered “hidden” from the host operating system.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: A method of providing conversion from YUV signals to RGB signals includes the steps of determining a correspondence value between each of the Y. U, and V pixel values and the corresponding one of the R, G, and B pixel values. Three tables are generated; a Y table, a U table and a V table. During operation, each table may then be easily accessed by indexing the table with the respective Y, U or V input, to provide R,G,B data. The method may be used in a 64 bit embodiment using two registers or one register. Alternatively, the method may be used in a 32 bit embodiment. The conversion method can easily be augmented to provide color adjustment during conversion without any added complexity.

Abstract: A computer including a computer housing having a processor and a number of peripheral devices operatively connected to the processor, a docking connector mounted on the computer housing and operatively connected to the processor, a reservation module operative to reserve one of a plurality of resources for use by a peripheral device operatively connected to a docking station that is operatively connectable to the docking connector, and an allocation module responsive to an indication from the reservation module operative to allocate the one of the resources to one of the plurality of peripheral devices.

Abstract: In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.

Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps. The other steps include receiving a next field, compensating the field in the input buffer, deinterlacing the received field with the compensated field in the input buffer, temporarily storing the received field, merging the received field and the compensated field into a video frame of the second sequence, and providing the video frame of the second sequence to a subsequent device.

Abstract: Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter.

Abstract: Improved techniques for monitoring behavioral data of components of a computer system are disclosed. The monitoring begins to monitor a component once a monitoring program recognizes the presence of the component within the computer system. Then, the monitoring program tracks behavioral data generated by the component. A user interacting with the monitoring program is thus able to monitor the operation of the component by analyzing the various behavioral data it receives from the component. In one embodiment, the component is a hardware resource and its driver sends events to the monitoring program, and the driver receives commands from the monitoring program.