Abstract: In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard. sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register.

Abstract: A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth.

Abstract: A home entertainment appliance includes a computer system and a television system. A video monitor or television monitor of the home entertainment system shows a sequence of video frames generated in the appliance based upon at least one received sequence of interlaced video fields each containing a number of scan lines. A video system of the appliance receives a first field, temporarily stores the first field in an input buffer, and then in a loop, while video fields are being received, performs various other steps. The other steps include receiving a next field, compensating the field in the input buffer, deinterlacing the received field with the compensated field in the input buffer, temporarily storing the received field, merging the received field and the compensated field into a video frame of the second sequence, and providing the video frame of the second sequence to a subsequent device.

Abstract: A network device with selectable traps that improves network management by enabling a system manager or administrator to select between multiple trap definitions. The network device includes a memory that stores a management database including a plurality of trap definitions and a programmable parameter for selecting any one of the trap definitions. The network device further includes management processing logic that executes a management agent that issues traps according a selected one of the trap definitions depending upon the programmable parameter. In the embodiment described herein, the management database includes the standard Ethernet.TM. Repeater MIB implemented according to RFC 1516 including a first trap definition and the Ethernet.TM. Hub MIB by Novell including a second trap definition. The management agent issues traps according to either one of the trap definitions depending upon the programmable parameter.

Abstract: Instruction issue logic is disclosed that assesses register availability. The issue logic comprises register scoreboard logic that includes destination register storage elements to identify destination registers of instructions queued for issue. An arbiter selects instructions for issue during a machine cycle from the queued instructions. Register-clean wires associated with each register are driven in response to the corresponding destination storage elements and the arbiter. These wires are used to identify the read-availability of registers. Specifically, such a logic system is capable of reflecting freed registers on the subsequent machine cycle so that previously issued instructions do not hinder queuing of new instructions, unless they require multiple cycles to complete. To increase speed of operation, single NMOS devices bridge the register-clean wires and the issue signal from the arbiter.

Abstract: An event notification system for a network including a managed device that includes one or more management agents that detect one or more management events of a plurality of possible management events. The managed device further includes event notification logic that generates an event notification message (ENM) which includes event related information. The ENM is written using a markup language, such as XML, to encode the event related information based on the management event. The ENM may include executable code written in a scripting language or the like, that when executed, causes at least one action to be performed. A management server is provided that includes an event processor that executes the code to perform the desired actions in response to the particular management event. The event related information may further include a URL to locate one or more information files in the network that provides further information about the management event.

Abstract: Improved techniques for monitoring behavioral data of components of a computer system are disclosed. The monitoring begins to monitor a component once a monitoring program recognizes the presence of the component within the computer system. Then, the monitoring program tracks behavioral data generated by the component. A user interacting with the monitoring program is thus able to monitor the operation of the component by analyzing the various behavioral data it receives from the component. In one embodiment, the component is a hardware resource and its driver sends events to the monitoring program, and the driver receives commands from the monitoring program.

Abstract: A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

Abstract: An encoded message, includes a plurality of data items and a plurality of redundant data items. Each of the plurality of redundant data items corresponds to a number of the data items, with respective redundant data items corresponding to different numbers of data items.

Abstract: A method and apparatus for inverse dithering a dithered image is disclosed. The system includes a plurality of digital filters which are organized according to a preselected order. A selection module enables the selection of one filter from the plurality of filters according to the preselected order to filter a presently selected portion of the dithered image. The selected portion of the dithered image is then processed based upon the selected filter to generate a portion of the inverse dithered image.

Abstract: An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.

Abstract: A technique for controlling an interactive presentation is disclosed. In one embodiment, a processing device receives at least one of a plurality of commands, wherein each of the plurality of commands corresponds to a respective operation the performance of which is directly associated with controlling a particular aspect of the interactive presentation. The processing device processes each of the received commands such that each corresponding operation is performed to control a particular aspect of the interactive presentation.

Abstract: A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register.

Abstract: A packet processing system or router is disclosed that has at least one central packet-header processor, a packet broadcast bus, and local packet controllers that communicate with each other and the central packet-header processor via the packet broadcast bus. Packets received by media access controllers are passed to the associated local packet controllers and then broadcast on the packet broadcast bus. These broadcast packets are stored in packet buffer memories of the controllers, and the processor snoops for at least headers of the broadcast packets. The headers are analyzed and the processor issues forwarding instructions concerning the broadcast packets to the local packet controllers. As a result, the packet data only traverses the bus once. Only a relatively short forwarding decision is generated after the packets are broadcast and this can occur on a separate control bus, if desired.

Abstract: A method for reducing power consumption in a computer system is provided wherein the computer system includes a system bus interface connected by a signal line to a power supply and/or clock circuitry for the central processing unit, each having the capability to change the characteristic of its output responsive to the signal line for placing the central processing unit in a low-power consuming state. The system bus interface chip further including a storage location and counter for storing the type and quantity of interrupt assertions during the period of time when the central processing unit is in the low power consuming state.The system software determines the desired period of time to put the central processing unit into the low-power consuming safe and does not return it to normal power consuming state until the time period has expired, a non interval clock interrupt is asserted, or another critical event occurs that needs immediate CPU attention.

Abstract: Metadata described herein on a RAID array includes both device metadata and RAIDset metadata. The device metadata has a device FE bit on each storage device corresponding to each RAID protected block on the storage device. The device FE bit indicates if a corresponding RAID protected block is consistent and thereby useable to regenerate data in another RAID protected block in the corresponding RAID protected block's sliver. The user data also has a forced error bit to indicate if a physical block in the user block has inconsistent data, the RAIDset FE bit. The RAID array of storage devices has user data blocks on each storage device RAID protected by being distributed as slivers of blocks across the RAID array of storage devices. Each sliver has a plurality of user data blocks and one parity block. The RAIDset metadata has the RAIDset FE bit corresponding to each RAID protected user data block in the RAID array.

Abstract: A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i.e., target address) is not the first address (i.e., initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit.

Abstract: A multiprocessor computer system is provided with a BIOS that allows parallel execution of system initialization tasks by at least two processors to reduce system boot-up time. At power-on, one of the processors is designated as a bootstrap processor and the remaining processors are designates as application processors. The processors are coupled to a shared memory module by a shared processor bus. The bootstrap processor is configured to instruct the application processor to test and initialize memory locations in the shared memory module while the bootstrap processor proceeds with other system initialization tasks which may include determining the system configuration, initializing peripheral devices, testing the keyboard, and setting up the BIOS data area with configuration information. After completing its tasks, the bootstrap processor determines whether the application processor has completed the memory test, and if so, the bootstrap processor proceeds to locate and execute an operating system.

Abstract: A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.