Abstract: A notebook computer has a collapsible keyboard in which elastomeric key switch domes on the top side of a dome sheet are horizontally shiftable under the keys to selectively underlie and support them for use, or to permit the keys to be collapsed to depressed positions to reduce the thickness of the keyboard in its storage and transport orientation. When the computer display housing lid is closed it contacts and pivotally depresses a small LCD status display structure supported on the top side of the computer base housing rearwardly of the keyboard and linked to the dome sheet in a manner such that the dome sheet is responsively shifted to collapse the keys.

Abstract: Piezoelectric speaker achieves radiation efficiency at low frequencies by using a piezoelectric speaker panel as a lumped parameter resonator. The speaker panel is mounted in a resonant system for generating translational motion. The resonant system includes suspension devices for suspending the panel to allow for translational motion of the panel and isolators for tuning the speaker panel to a predetermined frequency. At the predetermined frequency, the speaker panel achieves resonance in a low order mode, producing improved radiation efficiency at lower frequencies and translational motion of the panel not possible with a piezoelectric activator alone. The speaker panel may be included in a portable computer system, a desktop computer monitor, or other sound systems. In a portable computer system, a display screen or front speaker panel serves as a lumped parameter resonator, and the lid or rear speaker panel serves as a structure born vibration resonator.

Abstract: An apparatus supports both (1) a cost-effective graphics device (such as an AGP device) integrated onto the motherboard, and (2) an upgradable computer system with an add-in card slot for receiving a second graphics device (such as a second AGP device) on a card. The apparatus is connected to a bus that has a first set of signals which is sensitive to noise. The apparatus also has a first switch connected to a first device, the first switch being connected to the first set of signals on the bus. The apparatus has a second switch which is adapted to be connected to a second device. The second switch is also connected to the first set of signals on the bus. The apparatus also has a detector connected to the first and second switches to enable the first switch if the first device is selected and otherwise enable the second switch.

Abstract: A battery charging system in which current is averaged over a long time period (seconds) to determine the maximum average charging rate. When the integral of charging current over this long period reaches the programmed maximum charge value for one period, current is simply cut off for the remainder of the fixed long period.

Abstract: A computer having a control panel for directly controlling software and hardware of the computer, eliminating the necessity of navigating software to control such functions. These direct controls can include audio CD controls, telephone answering machine controls, instructional software controls, power setting controls, and volume controls.

Abstract: A computer system includes a chassis, a tray and a motherboard. The tray is configured to form a detachable connection with the chassis, and the motherboard is mounted to the tray.

Abstract: A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.

Abstract: The system and method of the present invention facilitate clamping of a land grid array integrated circuit (LGA IC) device through adjustment and calibration of the clamping system in relation to the connector/socket features used for a given type of LGA IC device and connector/socket. In order to accommodate for different connector/socket heights, the clamping system of the present invention includes exchangeable calibrated springs and an exchangeable shim that enable the clamping system to adjust to a specific connector/socket height. Due to the level of calibration, the system and method provides controlled downward vertical force at the level of force required to clamp the pads of the LGA IC device to the contacts of the connector/socket thereby providing complete electric contact therebetween and complete electric contact between the connector/socket and a circuit board.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A computer system includes a non-removable disk drive that has a capacity that may exceed 7.875 GB. The computer system generally includes a processor, a disk drive controller, a display, an input device, and a non-volatile memory device that includes firmware that is executed during system initialization. The storage capacity of the drive is reported by the drive in terms of numbers of cylinders, sectors, and heads during system initialization. In response, the firmware informs the operating system of the capacity of the drive. The firmware translates the reported cylinder and head numbers. If the reported capacity of the drive is equal to or greater than 4,032 gigabytes, the firmware limits the number of heads reported by the drive to a predetermined value. In accordance with another aspect of the invention, the capacity reported by the drive is compared to a threshold value.

Abstract: A computer system comprising an input/output device, a processor, a memory device, and a bridge logic device for interfacing the memory device to the processor and input/output device incorporates a refresh logic device for generating a memory refresh signal during suspend mode. Because the rate at which memory must be refreshed generally depends on the temperature of the memory device, the refresh logic varies the frequency of the refresh signal according to the temperature of the memory device, resulting in substantial power savings. In a preferred embodiment, the refresh logic uses a normal-rate refresh signal at the beginning of suspend mode and incrementally steps down the refresh rate as the memory temperature decreases. In other embodiments, the refresh logic incorporates a signal generator which produces a refresh signal at a frequency that varies according the output voltage from a temperature sensor or the temperature-sensitive resistance of a thermistor.

Abstract: A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Abstract: A notebook computer base housing has operatively disposed therein a CD ROM drive, a hard disk drive and a floppy disk drive, an AC/DC electrical power converter, a modem, a PCMCIA card bay structure and a battery. This internal provision of three drive units in addition to the other equipment within the base housing is facilitated from a space standpoint by the vertical stacking of the hard disk drive atop the CD ROM drive within the base housing. To dissipate the operating heat from these components within the base housing, a heat spreader plate is interposed between the CD ROM drive and the overlying hard disk drive, and the high heat-generating components--namely, the modem, the AC/DC converter, the PCMCIA card bay structure, and the computer processor--are closely grouped together, with the AC/DC converter in thermal communication with a second heat spreader plate.

Abstract: A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of inputs, thereby forming a plurality of input/output pairs. The encoder circuit also includes a priority assignment circuit coupling each input of the plurality of inputs to its associated corresponding output of the plurality of outputs. The priority assignment circuit assigns a priority to each input/output pair, such that an output, which corresponds to an input which receives an asserted bit, and which has a highest priority, provides an asserted bit while all other outputs provide bits that are not asserted. The priority assigned to each input can be dynamically updated within the priority assignment circuit. Updates of priority that shift the priority position by one or more inputs can be done all using the same circuit.

Abstract: A computer system utilizing multiple processes includes a semaphore for controlling exclusive access of a single process to a selected resource. The semaphore is implemented in the system input/output and controlled, at least in part, by an application specific integrated circuit (ASIC). When a process is attempting to acquire an I/O resource, a read is sent to the semaphore. If the resource is available the semaphore will have a first value, and the semaphore will return that first value to the process indicating that the process has acquired the resource. The ASIC will then change the semaphore value to a second value. If the resource is not available the semaphore will have the second value, and the semaphore will return the second value to the process indicating that the resource is not available.

Abstract: A drive bay opening in the front bezel portion of a tower type computer CPU unit is provided with a swing-out plastic access door. The door is pivotable between a closed position and a full open stop position in which it is outwardly pivoted more than ninety degrees away from its closed position. A specially designed concealed, break-away hinge structure removably interconnects the access door and front bezel portion and includes a pair of hinge arms projecting outwardly from the door and molded integrally therewith. Outer end tabs in the hinge arms have apertures therein that rotatably receive hinge pins within recessed pocket areas in the bezel. In the event that the access door is forcibly pivoted outwardly beyond its full open stop position, separate disconnect pins disposed laterally outwardly of the hinge pins act as cams that torsionally deflect the hinge tabs out of engagement with the hinge pins.

Abstract: A rack serviceable computer chassis for housing multiple computer modules. A rectilinear housing receives at least one module containing electrical components associated with a computer system which includes a planar right panel, a planar left panel, a planar bottom panel, a stationary planar top panel for covering non-rack serviceable components, and a sliding top panel integral to the housing for effectuating access to the at least one module and electrical components. The sliding top panel is located above the stationary top panel while in an open position. The rack serviceable chassis further includes a means for sliding the sliding top panel between the open position and a closed position, a means for supporting the sliding top panel while in the closed position, and a means for transitioning the sliding top panel between the open position and the closed position.

Abstract: A management server for a network that facilitates and performs programmable event driven processing including event detection logic that receives and processes any of a plurality of event notifications transmitted via the network and that invokes at least one corresponding construction. Each event notification corresponds to the occurrence of management events and supports registration of listeners of each management event. The management server further includes executable components that each performs a basic function and a construction editor that enables access of the plurality of executable components. The construction editor facilitates defining a relationship between the executable components to generate constructions and performs registration of the constructions with the event detection logic as a listener of management events. Each construction, when invoked, executes its components according to the defined relationship to perform at least one desired management operation.

Abstract: This disclosure presents a novel scheme for rate-based scheduling. In particular, this approach can be applicable to scheduling flows in computer networks such as ATM. It can also be used to provide weighted fair service in scheduling computer jobs. Unlike many of the methods commonly used for rate scheduling in network adapters, the present method allows to provide strict rate guarantees to all flows. A distinguishing feature of the present method is that it operates in the frequency domain, rather than in time domain.