Abstract: An array controller that cleans buffer memory as a background task. The controller includes a transfer buffer, a memory that stores an index or table indicating free and non-zero data sectors within the transfer buffer, and processing logic that uses the transfer buffer for data transfer operations, and when otherwise idle, that scans the index table for contiguous sections of free and non-zero data sectors of the transfer buffer and that zeroes at least one of the contiguous sections. The controller allocates buffer memory and performs parallel logic operations into the buffer, such as XOR logic operations to generate new parity data. The buffer must first be zeroed or cleaned prior to the parallel operations. With the background task, the controller is more likely to find an appropriate size buffer of free and zeroed data sectors in the transfer buffer to perform the parallel logic operations.
Type:
Grant
Filed:
November 4, 1997
Date of Patent:
January 22, 2002
Assignee:
Compaq Information Technologies Group, L.P.
Abstract: In a system for executing database queries, a directed graph of logically interconnected tasks represents an execution plan for executing a specified database query. A pair of queues are stored in a computer memory for each pair of interconnected tasks in the directed graph. One of the queues in each pair is a down queue for sending requests from a parent task to a child task, and the other is an up queue for sending replies from the child task to the parent task. Each queue is a circular buffer and includes a head pointer that points to a next location in the queue to be read, and a tail pointer that points to a next location in the queue in which data can be written. Each task checks that a queue is not full before writing data into that queue, and checks that the sibling queue is not empty before reading data from the sibling queue.
Type:
Grant
Filed:
September 24, 1998
Date of Patent:
January 22, 2002
Assignee:
Compaq Information Technologies Group, LP
Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Inter-instance communication can occur in at least two different ways.
Type:
Grant
Filed:
June 10, 1998
Date of Patent:
December 18, 2001
Assignee:
Compaq Information Technologies Group, L.P.
Inventors:
James R. Kauffman, Andrew H. Mason, Paul K. Harter, Jr.
Abstract: A portable notebook computer having a thickness of only one inch is obtained by provision of a computer housing containing a keyboard assembly and a motherboard positioned directly below the keyboard assembly, the keyboard assembly and the motherboard thereby defining a region in the enclosure. The other components comprising the computer; i.e. a hard disk drive, a PCMCIA option slot, a trackball assembly, and a DC to DC convertor, are positioned in an adjacent and generally co-planar relationship with this region. A battery housing is mounted externally on the computer housing for supplying electrical power to the computer.
Type:
Grant
Filed:
February 15, 2000
Date of Patent:
October 23, 2001
Assignee:
Compaq Information Technologies Group, L.P.
Abstract: A processor of a multiprocessor system is configured to transmit a full probe to a cache associated with the processor to transfer data from the stored data of the cache. The data corresponding to the full probe is transferred during a time period. A first tag-only probe is also transmitted to the cache during the same time period to determine if the data corresponding to the tag-only probe is part of the stored data stored in the cache. A stream of probes accesses the cache in two stages. The cache is composed of a tag structure and a data structure. In the first stage, a probe is designated a tag-only probe and accesses the tag structure, but not the data structure, to determine tag information indicating a hit or a miss. In the second stage, if the probe returns tag information indicating a cache hit the probe is designated to be a full probe and accesses the data structure of the cache. If the probe returns tag information indicating a cache miss the probe does not proceed to the second stage.
Type:
Grant
Filed:
June 18, 1998
Date of Patent:
September 25, 2001
Assignee:
Compaq Information Technologies Group, L.P.
Inventors:
Rahul Razdan, Solomon J. Katzman, James B. Keller, Richard E. Kessler
Abstract: A battery-powered computer chassis intrusion detection circuit which stores the time and date that the chassis hood, components, or AC power was removed. When intrusion occurs, an alarm bit isolates the detection circuit oscillator from the circuit, effectively stopping a real time clock from incrementing the time and date. When the computer is powered back up, internal ROM checks to see if an alarm condition occurred. If so, the intrusion date and time is recorded and the user or administrator may be alerted.