Abstract: A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. The technique further involves maintaining, in a vector memory circuit having bits that respectively correspond to the physical registers, a valid vector that forms, in combination with the list of register assignments, a list of valid register assignments. Furthermore, the technique involves storing, for an instruction that is mapped by the data processor, a copy of the valid vector from the vector memory circuit to a silo memory circuit. Preferably, the processor using the technique has the ability to execute branches of instructions speculatively, and to recover if it is determined that the processor executed down an incorrect instruction branch.

Abstract: An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data.

Abstract: A computer system having detection logic for detecting a hot-pluggable component module being added to the computer system. The detection logic determines when the hot-pluggable component module is fully inserted in a component connector, waits a predetermined time to insure that the hot-pluggable component module is properly seated in and electrical connections made to the component connector, and then notifies a hot-plug controller that a new component module is available for use in the computer system. The hot-pluggable component module, such as a memory module, may be used by the computer system as a replacement for a defective module, upgrade and/or addition without disturbing normal operation of the computer system.

Abstract: Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A computer system having PCI devices, associates bus numbers with these PCI devices during computer system configuration. During startup of the computer system, startup software relies on the bus numbers associated with the PCI devices to find and configure the PCI devices for normal computer system operation. When a PCI/PCI bridge is added to an existing PCI bus, a new PCI bus is created. This may cause the bus numbers of some of the PCI devices to change. Unless the computer system configuration is run again, normal operation of the computer system may not take place because the startup or “boot” program may not be able to find and configure the affected PCI devices without knowing the correct bus numbers. Adding the PCI physical connector slot number to the information derived during the system configuration and storing same in non-volatile RAM enables the computer system to update any PCI device bus numbers that may have changed without having to rerun the system configuration software.

Abstract: A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiprocessor system. A processor of the multiprocessor system is configurable to evict from its cache a block of data. The selected block may have a clean coherence state or a dirty coherence state. The processor communicates a notify signal indicating eviction of the selected block to the memory controller. In addition to sending a write victim notify signal if the selected block has a dirty coherence state, the processor sends a clean victim notify signal if the selected block has a clean coherence state.

Abstract: An apparatus and method is disclosed for providing 10BASE-T Ethernet compatible data communications between multiple network elements, such as computers, computer peripherals, computerized appliances, and the like, over a two wire residential phone line. Each network element may include a 10BASE-T compatible network interface card (NIC) for interfacing between the network element and the residential phone line through the device of the present invention. A transmit/receive switch, set to a default receive position, is coupled between the two wire residential phone line and a NIC, each NIC having a transmit and receive wire pair. The NIC senses receive energy originating from the residential phone lines. When receive energy is no longer sensed at the NIC, a transmit signal may be generated by the NIC, placed on the transmit wire pair.

Abstract: A system and method for maintaining a communications within a computer system after a data transport failure across a first link. Fail-over capability is attained by re-establishing communications across a secondary link using different transport mechanisms. Between two Input/Output Processors (IOPs) within a computer system, such as a server, a series of data transactions therebetween are queued until transaction completion. Upon detection of a failure condition between the IOPs across the first link, the IOPs engage fail-over mechanisms to preserve uncompleted data transactions until communications are re-established across the secondary link.

Abstract: Techniques used in communicating messages between processes are described using a shared message buffer pool and incoming message lists associated with each process. Associated with each process is message management information. Using the message management information, incoming messages to a process are retrieved, outgoing messages to another process are sent, and message buffers are allocated as needed from a free message buffer list. The free message buffer list is a shared resource from which processes obtain a free message buffer to send a message to another process. Access to the shared free message buffer list and process message lists is synchronized through discipline imposed upon updating and accessing various fields of the data structure without requiring a global locking mechanism for synchronization of shared resources.

Abstract: A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving-of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A receiver for receiving an analog signal that is digitally modulated using differential binary phase shift keying (DBPSK) and demodulated by a quadrature demodulator into two signals. The receiver converts the two signals into two digital signals using 2-bit analog-to-digital converters. Samples of these digital signals are then encoded according to a maximum likelihood criteria algorithm and decisions are made based on the signal constellation, which identifies the original data transmitted.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. A grouping of partitions, a community, shares memory. Memory may be private to a particular partition or may be shared by partitions within a community.

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: A method of preventing current hogging in parallel connected transformers, and an apparatus for efficiently implementing the method are presented. Current hogging occurs when synchronous power converter transformers operate in a low output current mode. Low output current demands are typically meet by adjusting the duty cycle of the transformer to a low level. This results in the catch FET maintaining a low resistance path to ground for long time periods and allows a stronger one of the parallel power converter transformers to sink current to ground through a weaker transformer. The method consists of using a current sensor to detect low or negative output currents, and then driving the transistor providing the path to ground to an off state.

Abstract: A technique handles load instructions within a data processor that includes a cache circuit having a data cache and a tag memory indicating valid entries within the data cache. The technique involves writing data to the data cache during a series of four processor cycles in response to a first load instruction. Additionally, the technique involves updating the tag memory and preventing reading of the tag memory in response to the first load instruction during a first processor cycle in the series of processor cycles. Furthermore, the technique involves reading tag information from the tag memory during a processor cycle of the series of four processor cycles following the first processor cycle in response to a second load instruction.

Abstract: An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The semiconductor device has a pad for receiving a signal. The technique uses an ESD protection circuit that includes a voltage limiter having an input to receive a control voltage that is independent of a pad voltage on the pad; an output to provide, in response to the control voltage, a limited voltage having a magnitude that is less than a magnitude of the control voltage when the control voltage is non-zero and in a steady state; an arrangement of stacked transistors interconnected between the input and the output of the voltage limiter; and a pull-up transistor that is interconnected between the pad and the output of the voltage limiter. A magnitude of the pad voltage is less than the control voltage when the semiconductor device is in a normal operating mode.

Abstract: A computer system comprises a variety of components transmitting variable-rate heartbeats to a heartbeat monitor, each heartbeat indicating that the component is functioning properly. In addition, selected components serve as proxies by transmitting heartbeats to indicate that another component is functioning properly. In the preferred embodiment, one or more central processing units (CPUs) transmit heartbeats to indicate proper CPU functioning, while a bridge logic device and a network interface card (NIC) transmit heartbeats as proxies for a memory device and an external computer system, respectively. The heartbeat monitor is capable of determining initial heart rates for each component and is further capable of adaptively varying the heart rates thereafter. If the age of the heartbeat sender is relatively young, then a relatively slow heart rate is specified. Faster heart rates are specified for older components.

Abstract: A method and apparatus for presenting the multiple processors of a cluster as a single virtual host to a network wherein the processors are communicatively coupled among themselves and to a network interface. The network interface is communicatively coupled to the network. One of the processors is designated a primary parallel I/O processor. One address is advertised on said network for said multiple processors, and filter trees in the network interface direct the interface to forward packets from the network addressed to that address to the primary parallel I/O processor. Later, the filter tree is modified to direct the network interface to forward a specific subset of the packets directly to a particular processor.