Abstract: A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation.

Abstract: A system and method to reduce power. consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive, is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A computer convergence system includes a convergence functionality module, a computer, and a display device. The convergence functionality module includes a first input for receiving a first video signal and a second input for receiving a second video signal. The computer is coupled to the convergence functionality module and receives therefrom indications of the first video signal received at the first input port and indications of said second video signal received at the second input port. The computer includes a controller for controlling the mapping of the indications of the first video signal to the primary video viewing surface, and further controls the mapping of the indications of the second video signal to either the second video viewing surface or the data acquisition destination.

Abstract: A computer system includes a graphics controller with a first refresh rate and a first horizontal synchronization signal; a secondary source of video data having a second refresh rate and a second horizontal synchronization signal; and a genlock unit for reconciling the first refresh rate of the graphics controller with the second refresh rate of the secondary source. The genlock unit outputs a clock signal with a frequency modulated to reconcile the first refresh rate and the second refresh rate by monitoring the phase differences of the first horizontal synchronization signal and the second horizontal synchronization signal in response to a first control signal and outputs a clock signal at a frequency corresponding to a selected clock frequency in response to a second control signal.

Abstract: A computer system is implemented according to the invention when priority information is included with a bus transaction. Instead of processing bus transactions on a first-come-first-served basis, a computer peripheral device can make decisions about the relative importance of a transaction and process the most important ones first. The priority scheme can be based upon the priority of the process that generates the transaction or on any other scheme. Included in the invention is logic to ensure that transactions of low relative priority do not get completely ignored during periods of high activity.

Abstract: An improved MOS IC is disclosed having a low standby current ESD voltage clamp for the power and ground pads. The ESD voltage clamp uses the vertical PNP transistors inherently available in CMOS device fabrication by using the P+ source drain regions as the emitter, the N+ source drains as base contacts, the N wells as bases, and the P substrate as collectors. Thus the advantages of rapid voltage spike protection may be obtained with no increase in the number of masking steps or device fabrication complexity. The vertical PNP bipolar transistors are arranged in a Darlington configuration with the last transistor in the chain having a base region connected to both a resistor charging network connected to the power supply, and a capacitive network connected to the ground potential. A PMOS transistor is attached across the emitter and base of the last bipolar transistor in the Darlington chain to reduce the voltage overshoot and regulate the charge on the capacitor network.

Abstract: A method and apparatus are provided for refining time alignments of closed captions. The method automatically aligns closed caption data with associated audio data such that the closed caption data can be more precisely indexed to a requested keyword by a search engine. Further, with such a structure, the closed captions can be made to appear and disappear on a display screen in direct relation to the associated spoken words and phrases. Accordingly, hearing impaired viewers can more easily understand the program that is being displayed.

Abstract: A computer system has a ROM device containing two separately flashed areas. Each area contains a firmware image. From the factory, the two firmware images are identical. Each image also contains the executable code to flash an image area. The ROM also contains a “boot block” sector that makes decisions as to which of the firmware images is the “active” image and which is the “inactive” image. The active image is copied from the ROM to a RAM device and executed from RAM during normal system operation. The inactive image normally is not executed. The boot block sector also contains code that performs a checksum verification on the active image during initialization and, if the checksum fails, switches the active/inactive status of the two firmware images to make the previously inactive image the active image. With two firmware images, the system can recover from a power failure occurring while flashing the ROM because the other firmware image is still available.

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: A self-contained portable networked computer system having integral storage, power and communications for all components of the networked computer system. The networked computer system comprises a network server fabricated within the walls of a carrying case also having compartments for storing portable (clamshell style) workstations and necessary cabling for power and communications to these workstations. The carrying case may be a brief case, a sample case, a suitcase, a metal case, a fiberglass case, a plastic case or any other type of case used for storage and transporting of papers, and/or equipment. The case may be small enough to slide under an airplane seat or be as large as a steamer trunk. The case may be waterproof, bullet proof, airtight, lockable, etc. The case may also be located in a transportation vehicle or a piece of furniture.

Abstract: A system and method for identifying free registers within a program. A depth first search of a flow diagram representing the execution of a program is performed. The search proceeds simultaneously for all the registers and identifies the free registers from the search. The free registers may then be utilized for various applications without saving and restoring the contents of these registers to memory. The system may limit the amount of time spent searching for free registers with a timer.

Abstract: An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: A computer system allows resuming from Power-On Suspend (POS) mode by generating an interrupt. The interrupt generates a System Management Interrupt (SMI), which a controller uses to produce a POS resume event signal to resume the system from the Power-On Suspend mode. The system allows use of chipsets such as the VIA VT82C586B that are incapable of directly causing a resume from POS mode in response to an interrupt.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands and a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed. In addition, the system includes storage containing domain information defining groups of entities, where the kernel may issue a command to a group by issuing individual commands to appropriate modules.

Abstract: A housing for a central processing unit including a body capable of supporting and enclosing the central processing unit. The body has a front side including an upper portion and a lower portion. A first decorative faceplate is for detachably engaging with at least a portion of the upper portion of the front side of the body. A first-faceplate-quick-connect-device extends from the first decorative faceplate for readily attaching and removing the first decorative faceplate to the body. Also described herein is a housing for a central processing unit including a body capable of supporting and enclosing the central processing unit. The body has a front side including an upper portion and a lower portion. A first decorative faceplate is detachably engagable with at least a portion of the upper portion of the front side of the body. A second decorative faceplate is for detachably engaging with at least a portion of the lower portion of the front side of the body.

Abstract: A fan assembly that can be easily inserted into a mating slot includes: a housing surrounding and supporting a fan, a least one grill positioned so as to restrict access to the fan, a grip surface on the housing, a latch on the housing and configured to engage the mating slot; and, and an electrical connector mounted in the housing. The grip surface is formed on a separate piece from the housing and is affixed to the housing by an integrally formed fastening device and the assembly including the housing, grill, grip surface, latch and connector can be assembled by hand without the use of separate fasteners.

Abstract: A distributed computing system environment includes multiple CPUs, multiple non-shared memory spaces and a means for implementing system calls and interprocess communications. The system is both fault-tolerant and scalable in that agents exist independently in each non-shared memory space to handle interprocess connections between memory spaces.

Abstract: A method and apparatus for reducing latency caused by cumulative point-to-point messaging associated with network performance monitoring in SAN-attached I2O architectures. In a computer system, a performance monitoring OSM associated with a first node generates status request messages to a first multicast ISM residing on a first governor IOP associated with a first node for requesting the status from all nodes. The first multicast ISM generates status request messages to all node 1 devices and node 1 IOPs and to a second multicast ISM residing on a node 2 governor IOP. The second multicast ISM generates status request messages to all node 2 devices and node 2 IOPs. One or more “unhealthy” device response messages may be sent to the performance monitoring OSM containing the TID of the “unhealthy” device to allow a subsequent point-to-point detailed status request message to be issued.