Abstract: A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art.

Abstract: A method and system of interchassis and intrachassis computer component command and control. The existing power rail is used for network connectivity for intrachassis command and control. An existing common power mains can be used for interchassis command and control. Further, a protocol, for example, the Consumer Electronic Bus (CEBus) protocol (or a CEBus protocol modified for the particular power rail) can be used to provide interchassis and intrachassis platform management functionality. This management functionality is similar to that provided by the proposed Intelligent Platform Management Interface (IPMI) specification. A chassis bridge controller is used to interface the intrachassis power rail command and control infrastructure to an exterior network. External systems (interchassis communications) can communicate to the bridge via the particular protocol over an existing common power mains as a secondary channel exterior network.

Abstract: A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack.

Abstract: A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction.

Abstract: An innovative security system in which the need to “unlock” the system is eliminated if the system is awakened within a predetermined duration from its last use. In the preferred embodiment, when the user “logs onto” a system by activating it and entering his password, the time of login, plus a predetermined delay, is stored in nonvolatile memory. Thereafter, if the system is placed (or places itself) into a low-power mode, no password will be required to log onto the system if the logon is made before the time stored in nonvolatile memory. If the logon is attempted after this time, the user must go through the entire authorization procedure.

Abstract: A computer system permits the use of a software-based power management system, such as ACPI, while maintaining compatibility with legacy peripherals. The computer system utilizes a sleep register and a decoy register that receive sleep requests from the operating system. The sleep type bits transmitted to the sleep register are configured to allow the computer system to remain in fully operational mode, and only the decoy register receives the correct sleep type bits from a sleep request. When a sleep enable bit in the decoy register is set by a sleep request, an SMI is generated to run an interrupt service routine to perform any desired configuration routines prior to sleep mode. The interrupt service routine then writes the true sleep type bits to the sleep register, placing the computer system into sleep mode. The sleep enable bit resides in the highest byte of the decoy register so that byte-wide write operations do not trigger the SMI before the entire 16-bit sleep request is received.

Abstract: The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

Abstract: A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_CLOCK state, the sub-unit periodically transmits bursts of clock signals to signal the other sub-unit that it is powered up.

Abstract: An expansion base with a rearward-emitting expansion speaker for emitting low frequency audio and providing surround sound capability. The frequency response of the expansion speaker includes subwoofer frequencies, and is also extended to 600 Hz or higher, to enhance surround sound and spatial impression effects.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A system with a plurality of devices compatible with the Fiber Channel Protocol, with at least one initiator/originator and one target/responder. The initiator/originator is provided with the capability to send both data and command frames to the target/responder to increase write performance. The target/responder allocates a portion of its Responder-Exchange-Identifiers for the write use of the initiator/originator, which manages the use of these identifiers.

Abstract: A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues.

Abstract: An apparatus is used to identify the type of microprocessor assembly mounted on a printed circuit board. A heat sink is coupled to the microprocessor assembly, and a label is coupled to the heat sink. The label has one of a plurality of preselected patterns of optically reflective and non-reflective areas formed thereon, and at least one photodetector is positioned adjacent the microprocessor assembly on the printed circuit board for detecting the preselected pattern.

Abstract: An apparatus for mounting a display includes a tray having an end and a back plate pivotably mounted to the tray proximate the end. An apparatus in accordance with another aspect of the invention includes a cabinet, a pivotable display assembly, and a keyboard assembly. The cabinet has mounting rails. The pivotable display assembly includes a display tray having an end and being mounted to the mounting rails and a back plate pivotably mounted to the tray proximate the end. The keyboard assembly includes a keyboard tray and a keyboard slide having fixed and moveable portions. The fixed portion is mounted to the mounting rails, and the moveable portion is mounted to the keyboard tray. The switchbox is mounted to the fixed portion of the keyboard slide.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping “fill” requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the “victim” data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.

Abstract: A computer having a control panel for directly controlling software and hardware of the computer, eliminating the necessity of navigating software to control such functions. These direct controls can include audio CD controls, telephone answering machine controls, instructional software controls, power setting controls, and volume controls.

Abstract: A rectifier comprising a current transformer configured to receive a bipolar signal. The current transformer is comprised of a primary coil and preferably two secondary coils with opposite polarities. The rectifier also includes a rectifying transistor coupled to one of the secondary coils in the current transformer. Positive current from the first secondary coil causes the transistor to turn on thereby allowing current to flow through the transistor from the input of the rectifier to the output of the rectifier. A pull-down transistor is coupled to a second secondary coil of the current transformer. Positive current from the second secondary coil causes the pull-down transistor to turn on. The pull-down transistor is configured to connect the control terminal of the rectifying transistor to ground, thereby turning the rectifying transistor off, when the pull-down transistor is turned on.

Abstract: A heat dissipating apparatus for use on a heat generating electric component inside a computer comprises an interposer mounted on the heat generating electric component and a heat absorbing member including a heat absorber, a bracing member, and a spring biasing said heat absorber toward the bracing member. The heat absorbing member is moveable between a first position in which the interposer is compressed between the heat absorber and the bracing member and a second position in which the interposer is not compressed between the heat absorber and the bracing member.

Abstract: A memory management system couples processors to each other and to a main memory. Each processor may have one or more associated caches local to that processor. A system port of the memory management system receives a request from a source processor of the processors to access a block of data from the main memory. A memory manager of the memory management system then converts the request into a probe command having a data movement part identifying a condition for movement of the block out of a cache of a target processor and a next coherence state part indicating a next state of the block in the cache of the target processor.

Abstract: A method is provided for processing an input command for a handheld computing device, comprising the steps of: measuring movement of the device over an interval of time with a motion sensor mounted to the device to generate a signal; analyzing the signal measured over the interval of time to determine a gesture command that corresponds to the movement of the device; and processing the gesture command to control the device as of an orientation of the device at the beginning of the interval. In addition to gesture commands, position commands can be input. Position commands are processed by measuring of a series of orientations of the device, analyzing the signal to determine a series of position commands that correspond to the series of orientations of the device, and processing the series of position commands to control the device. The method of processing of gesture commands avoids confusion due to inappropriate processing of orientations falsely determined to be position commands.