Abstract: A method for performing an atomic read of a memory cell. A plurality of data parts of the memory cell are loaded into a respective first plurality of registers and an atomic compare and exchange operation is executed on the memory cell. The first plurality of registers is read and concatenated forming a value equal to the value of the memory cell. In a first embodiment, a low-order data part of the memory cell is loaded into registers A and B and a high-order data part of the memory cell is loaded into registers D and C. An atomic compare and exchange operation is executed on the memory cell and register A and register D are read and concatenated. In a second embodiment, the contents of register A is loaded into register B and the contents or register D is loaded into register C. An atomic compare and exchange operation is executed on the memory cell and register A and register D are read and concatenated.

Abstract: A computer system, bus interface unit, and method is provided for programmably modifying securable resources of the computer. Those resources may be devices which can be coupled to peripheral buses of the computer, or which may contain or allow access to sensitive information that must be secured against improper access. The security system thereby functions to block accesses to certain devices based on the status of the user seeking access. Passwords stored in the security system are matched against locally and distally entered passwords from either the user of that particular computer system, an administrator of a subset of localized computer systems, or a system administrator in charge of all networked computer systems. The present security system is thereby hierarchical in nature and can be programmed by the system administrator such that the assignment of unlocked signals arising from password comparisons can be programmably mapped to various securable devices.

Abstract: A break event in a computer system that can operate in one of a plurality of modes, such as a high performance mode and a low power mode is initiated only be logic that that detects when the transition between modes is complete. In the high performance mode, the CPU clock is faster than in the low power mode. The CPU voltage may also be higher in the high performance mode than in the low speed mode. The low power mode may be desirable for a portable computer operating from battery power in order to conserve the battery's charge. The computer system preferably transitions its CPU to a “sleep” state during the mode switch and precludes devices not associated with the mode transition from “waking” the CPU and disturbing the completion of the mode switch. Accordingly, only logic that detects the end of the mode switch can break the CPU out of its sleep state.

Abstract: A computer system is used with a telephone that is operable by a user to furnish a predetermined command. The processing unit and a control circuit. The central processing unit is connected to communicate with the interface port, and the control circuit is connected to the telephone. The control circuit is configured to detect the predetermined command and in response to detection of the predetermined command, change a connection status between the telephone and the interface port.

Abstract: A computer system allows devices to be unmasked so to be detected or to be masked invisible to the Plug-and-Play architecture or similar architectures. When operating under Plug-and-Play, which assigns systems resources to system devices in a predetermined order despite a limited number of such resources, a user uses software to set the switch in the device's memory such that an undesired device becomes “invisible” to a subsequent power-up configuration of the system. Device configuration proceeds in two phases. During a first configuration phase, the invisible device cannot be configured, i.e. cannot be assigned resources, including interrupt request lines. Hence, those lines remain available to other devices on the system that would not have received resource allocation during a prior-art configuration. During the first phase, the other devices can be assigned the necessary resources to operate properly. Thus, software can command a configuration that would otherwise be impossible.

Abstract: A portable notebook computer having a thickness of only one inch is obtained by provision of a computer housing containing a keyboard assembly and a motherboard positioned directly below the keyboard assembly, the keyboard assembly and the motherboard thereby defining a region in the enclosure. The other components comprising the computer; i.e. a hard disk drive, a PCMCIA option slot, a trackball assembly, and a DC to DC convertor, are positioned in an adjacent and generally co-planar relationship with this region. A battery housing is mounted externally on the computer housing for supplying electrical power to the computer.

Abstract: A connection technique for switchably and mutually exclusively coupling a plurality of device sets. The connection technique utilizes a low profile connector having multiple circuit sets, each of which is configured for mutually exclusive and removable insertion into a receptacle coupled to multiple devices. Each one of the multiple circuit sets, which is inserted into the receptacle, couples a desired set of the plurality of device sets.

Abstract: In a first aspect, the invention is a method for interfacing a generic program with the ASL code in an ACPI system. The method comprises storing information from a generic program in a shared memory; accessing the ASL code; and retrieving the stored information with the ASL code. In a second aspect, the invention is a method for testing ASL PnP code in an ACPI system. The method comprises identifying a configurable PnP device; disabling the identified configurable PnP device; testing the disabled, configurable PnP device for a configuration; and verifying that, for the tested configuration, the resulting current resources match the set resources. In variations of these aspects, the methods may be performed by instructions encoded on a computer-readable, program storage medium and used to program a computer.

Abstract: The SQL compiler and SQL executor in a database management system are extended to execute statements for dequeuing rows from a database table and statements that both updating tuples and return those tuples to a calling application. During execution of a select statement that includes an embedded update or delete operation, a table access operator accesses a defined range of rows in a database table. The table access operator receives from a calling application a request for rows dequeued from the database table. The table access operator responds to the requests for rows by returning to the calling application qualifying rows, if any, from the database table and also by performing the embedded delete or update operation. The SQL executor returns control to the calling application only after all rows deleted or updated by the table access operator have been sent to the calling application.

Abstract: In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.

Abstract: A computer system adapted for hot-pluggable components such as memory modules that may be replaced, upgraded and/or added without disturbing normal operation of the computer system. A failing memory module may be replaced by copying its contents to a new memory module in a background operation while the computer system runs its operating system and applications programs. When all contents are copied to the new memory module, the failing memory module may be removed without having to shut down the computer system. Computer system memory may be upgraded or added to by inserting the new memory module(s) into vacant disconnected memory connectors, whereupon the computer system automatically recognizes the new memory module(s), synchronously connects the new memory module(s) to the computer system memory bus, initializes the new memory module(s), and then notifies the operating system that the new memory module(s) is available, all without disturbing normal operation of the computer system.

Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Abstract: A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. Alternate embodiments of the present invention utilize a side-band address port (SBA port) to enable multiple targets to receive the same set of data. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction.

Abstract: A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. The generated multiple instructions are generated such that each of the generated multiple instructions executes using no more than two input ports of an execution unit. The generated multiple instructions include a first generated instruction that produces a condition result indicating whether a condition exists, and a second generated instruction that inputs the condition result as a portion of an operand which identifies a register of the out-of-order data processor.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: Each node of a multiprocessor computer system includes a main memory, a cache memory system and logic. The main memory stores memory lines of data. A directory entry for each memory line indicates whether a copy of the corresponding memory line is stored in the cache memory system in another node. The cache memory system stores copies of memory lines and cache state information indicating whether the cached copy of each memory line is an exclusive copy. The logic of each respective node is configured to respond to a transaction request for a particular memory line and its corresponding directory entry, where the respective node is the home node of the particular memory.

Abstract: A method for undeleting files in a computer system includes flagging at least one deleted file with an identifier. The flagged deleted file is hidden in the computer system. A list of deleted files that have been flagged with the identifier is generated. The list of deleted files is comprised of a directory path hierarchy for each deleted file. A file is selected from the list of deleted files and undeleted.

Abstract: A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation.

Abstract: A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell.

Abstract: A system and method to reduce power. consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive, is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.