Abstract: A method and apparatus are provided for refining time alignments of closed captions. The method automatically aligns closed caption data with associated audio data such that the closed caption data can be more precisely indexed to a requested keyword by a search engine. Further, with such a structure, the closed captions can be made to appear and disappear on a display screen in direct relation to the associated spoken words and phrases. Accordingly, hearing impaired viewers can more easily understand the program that is being displayed.

Abstract: A computer system has a ROM device containing two separately flashed areas. Each area contains a firmware image. From the factory, the two firmware images are identical. Each image also contains the executable code to flash an image area. The ROM also contains a “boot block” sector that makes decisions as to which of the firmware images is the “active” image and which is the “inactive” image. The active image is copied from the ROM to a RAM device and executed from RAM during normal system operation. The inactive image normally is not executed. The boot block sector also contains code that performs a checksum verification on the active image during initialization and, if the checksum fails, switches the active/inactive status of the two firmware images to make the previously inactive image the active image. With two firmware images, the system can recover from a power failure occurring while flashing the ROM because the other firmware image is still available.

Abstract: Guard prediction apparatus for predicting guard outcomes for predicated instructions, each of which specifies a guard operator to be applied to a guard source to generate the guard outcome. The guard prediction apparatus includes a cache, availability logic, a selection circuit, a deduction circuit and write back circuitry. The cache stores previous predictions of guard outcomes for a set of guard sources and guard operators. The availability logic determines whether the cache includes a previous prediction that is relevant to a first guard source and a first guard operator and, if so, couples that previous prediction to the selection circuit. The selection circuit generates the final guard outcome prediction by selecting between the previous prediction, if available, and an initial prediction, if a previous prediction is not available. The deduction circuit deduces from the initial prediction of the guard outcome other consistent guard outcomes for a set of guard operators when applied to the guard source.

Abstract: A method and apparatus for discovering, identifying and graphically representing network devices on a network. The devices are discovered by obtaining the gateway address of the management workstations and then reading the internet protocol address table and the ARP cache from each gateway via SNMP. Each address read is compared with existing IP addresses, and if new, device IDs are created and assigned. Select attributes are then assigned to each device and then the devices are then identified. The devices are identified by making a DNS request on the corresponding IP address to determine the network name of the device. The SNMP then obtains the system name and object ID (OID) for each of the devices. The OID is then compared and matched with known OIDs to identify the device. the devices are graphically connected and laid out by creating a submap based on the IP address and mask pairs for each device. The routers connected, the bridges are then connected and finally the repeaters are connected.

Abstract: A computer convergence system includes a convergence functionality module, a computer, and a display device. The convergence functionality module includes a first input for receiving a first video signal and a second input for receiving a second video signal. The computer is coupled to the convergence functionality module and receives therefrom indications of the first video signal received at the first input port and indications of said second video signal received at the second input port. The computer includes a controller for controlling the mapping of the indications of the first video signal to the primary video viewing surface, and further controls the mapping of the indications of the second video signal to either the second video viewing surface or the data acquisition destination.

Abstract: A computer system is implemented according to the invention when priority information is included with a bus transaction. Instead of processing bus transactions on a first-come-first-served basis, a computer peripheral device can make decisions about the relative importance of a transaction and process the most important ones first. The priority scheme can be based upon the priority of the process that generates the transaction or on any other scheme. Included in the invention is logic to ensure that transactions of low relative priority do not get completely ignored during periods of high activity.

Abstract: An improved MOS IC is disclosed having a low standby current ESD voltage clamp for the power and ground pads. The ESD voltage clamp uses the vertical PNP transistors inherently available in CMOS device fabrication by using the P+ source drain regions as the emitter, the N+ source drains as base contacts, the N wells as bases, and the P substrate as collectors. Thus the advantages of rapid voltage spike protection may be obtained with no increase in the number of masking steps or device fabrication complexity. The vertical PNP bipolar transistors are arranged in a Darlington configuration with the last transistor in the chain having a base region connected to both a resistor charging network connected to the power supply, and a capacitive network connected to the ground potential. A PMOS transistor is attached across the emitter and base of the last bipolar transistor in the Darlington chain to reduce the voltage overshoot and regulate the charge on the capacitor network.

Abstract: A customer information control system (CICS) application programming interface (API), with transient data queue functions, in a loosely coupled data processing environment. In accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed to a method, system and computer readable medium including program instructions (hereafter collectively referred to as the “invention”). In particular, the invention includes implementing a loosely coupled CICS region in a data processing environment, the loosely coupled CICS region including at least two of a plurality of address spaces each of which being associated with a machine. The invention further includes providing at least one CICS-API operating system server (COSS) within the loosely coupled CICS region, each COSS operating in one of the at least two address spaces within the loosely coupled CICS region.

Abstract: A hot-pluggable disk drive is supported on a carrier structure that is slidably and removably insertable rearwardly into a sheet metal cage portion of a computer system to releasably couple an SCA connector on the rear end of the drive to a corresponding electrical connector on a backplane structure within a rear interior portion of the cage. The carrier structure includes a base wall upon which the disk drive rests, and a pair of transverse side walls disposed on opposite side edge portions of the base wall. To substantially reduce self-induced, performance degrading operational vibration of the inserted drive about the rotational axis of its platter section, outward projections are formed on the opposite side wall portions of the carrier in a forwardly offset relationship with the rotational axis of the drive. As the drive is inserted into the cage, these projections slidingly engage and form an interference fit with inwardly bent opposing side wall portions of the cage.

Abstract: A method schedules execution contexts in a computer system based on memory interactions. The computer system includes a processor and a hierarchical memory arranged in a plurality of levels. Memory transactions are randomly sampled for a plurality of contexts. The contexts can be threads, processes, or hardware contexts. Resource interactions of the plurality of contexts is estimated, and particular contexts are chosen to be scheduled based on the estimated resource interactions.

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: A fan assembly that can be easily inserted into a mating slot includes: a housing surrounding and supporting a fan, a least one grill positioned so as to restrict access to the fan, a grip surface on the housing, a latch on the housing and configured to engage the mating slot; and, and an electrical connector mounted in the housing. The grip surface is formed on a separate piece from the housing and is affixed to the housing by an integrally formed fastening device and the assembly including the housing, grill, grip surface, latch and connector can be assembled by hand without the use of separate fasteners.

Abstract: A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.

Abstract: A notebook computer has a keyboard including a deflectable base plate on the top side of which a series of parallel rows of depressible key structures are operatively mounted. The base plate is structurally reinforced, without increasing the overall height of the keyboard, using elongated stiffening ribs disposed within the interior of the keyboard. The ribs longitudinally extend parallel to the key rows, are anchored beam-like to the top side of the base plate, and are interdigitated with the key rows.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands and a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed. In addition, the system includes storage containing domain information defining groups of entities, where the kernel may issue a command to a group by issuing individual commands to appropriate modules.

Abstract: An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter.

Abstract: A system and method for identifying free registers within a program. A depth first search of a flow diagram representing the execution of a program is performed. The search proceeds simultaneously for all the registers and identifies the free registers from the search. The free registers may then be utilized for various applications without saving and restoring the contents of these registers to memory. The system may limit the amount of time spent searching for free registers with a timer.

Abstract: A self-contained portable networked computer system having integral storage, power and communications for all components of the networked computer system. The networked computer system comprises a network server fabricated within the walls of a carrying case also having compartments for storing portable (clamshell style) workstations and necessary cabling for power and communications to these workstations. The carrying case may be a brief case, a sample case, a suitcase, a metal case, a fiberglass case, a plastic case or any other type of case used for storage and transporting of papers, and/or equipment. The case may be small enough to slide under an airplane seat or be as large as a steamer trunk. The case may be waterproof, bullet proof, airtight, lockable, etc. The case may also be located in a transportation vehicle or a piece of furniture.