Abstract: A system and method for providing soft modem and soft audio copy protection for hardware interfaces and software code utilized in an AC '97 architecture to prevent against unauthorized copying. The system confirms that a codec connected to the AC '97 architecture is provided by a desired supplier. The system performs a sample rate negotiation to determine an operating sample rate for data transfer. When the system provides a desired sample rate which does not correspond to a sample rate appearing in a predefined set of sample rates supported by an AC '97 architecture, the system expects the codec to echo back a predesignated sample rate during the sample rate negotiation indicating that a desired sample rate has been received which does not correspond to one of the supported sample rates.

Abstract: Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits.

Abstract: A filter system comprising three or more filters, each having different passbands, and an impedance adjusting network coupled between a filter system ports and each of the ports of at least two of the filters to adjust the port impedances of the filters coupled to the network. The adjusted port impedance of each filter at a frequency representative of at least one of the other filters coupled to the network is at a non-loading level. In one embodiment, the filter system is configured for use in a wireless communication receiver and/or handset.

Abstract: There is provided a speech decoder comprising a means for generating an excitation signal and a means for performing harmonic analysis and synthesis on the excitation signal in order to generate a smooth, periodic speech signal. The speech decoder further comprises a mixing means for mixing the excitation signal with the smooth, periodic signal and a synthesizing means for synthesizing the modified excitation signal into a speech signal that can be played to a user through a listening means. There is also provided a receiver that incorporates a speech decoder such as the decoder described above as well as a method for speech decoding.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle.

Abstract: This invention provides a charge pump biasing circuit that varies the bias when the phase lock loop changes frequency to improve the settling time of the phase lock loop. During a frequency change, the charge pump output current taper off as the phase lock loop approaches the desired frequency. The charge pump biasing circuit allows the phase lock loop to change frequencies faster and minimizes spurious sideband noise once the loop has settled.

Abstract: A system and method for performing a digital subscriber line (DSL) transmission over an AC-link bus directly connecting a modem codec to a codec controller. The codec and codec controller connected to the AC-link bus are configured for a particular industry-defined AC-link bus protocol defining a data packet having multiple time-division multiplexed (TDM) data slots, where the present invention redefines the protocol of the AC-link bus in order to allow a high bandwidth DSL transmission to be performed using the data packets transmitted over the AC-link bus. The present invention redefines the AC-link bus protocol to provide at least one additional TDM data slot in the data packet for handling DSL modem transmission data streams. The reconfigured data packet provides additional bandwidth capabilities which allow high-bandwidth DSL modem transmissions to be sent in the data packets transmitted over the AC-link bus, which where not previously achievable using the industry-defined AC-link protocol.

Abstract: There is provided a conference bridge or transcoder configured to intelligently handle multiple speech channels in the contest of a packet network, wherein various speech channels may adhere to variety of speech encoding standards. For example, the conference bridge establishes framing and alignment of multiple incoming speech channels associated with multiple participants, extracts parameters from the speech samples, mixes the parameters, and re-encodes the resulting speech samples for transmission to the participants. In one aspect, a speech processing method comprises decoding a first bitstream according to a first coding scheme to generate first speech samples and a first side information; generating second speech samples and a second side information using the first speech samples and the first side information, for use according to a second coding scheme; and creating a second bitstream, encoded based on the second coding scheme, using the second speech samples and the second side information.

Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: A system is disclosed for interfacing a wireless communication device baseband module and a radio frequency integrated circuit. The system accepts a control signal from the baseband module. The control signal from the baseband module is generally at a first baseband voltage. The first baseband voltage is generally the baseband operating voltage level. The system distributes the control signal, via data latches, to a plurality of local level shifters. The plurality of local level shifters are associated with components of the radio frequency integrated circuit. The local level shifters convert the control signal to a shifted control signal at a second voltage level. The second voltage level is generally the component operating voltage. The shifted control signal may be maintained at the component while the radio frequency integrated circuit is intermittently shutdown. The system eliminates the need to reprogram radio frequency integrated circuit components after the shutdown period.

Abstract: An improved thin-film capacitor and methods for forming the same on a surface of a substrate are disclosed. The capacitor includes a bottom conducting plate formed by depositing conductive material within a trench of an insulating layer and planarizing the conducting and insulating layers. A dielectric film is then deposited on the substrate surface, such that at least a portion of the dielectric material remains over the bottom conducting plate. The dielectric film is formed by depositing a first layer of dielectric and then immersing the top of the first layer of dielectric in gaseous plasmas in a single or a series of steps to change the composition of the first layer of deposited dielectric stack. The additional steps of immersion in a plasma is used to improve the desired performance of the dielectric for capacitor applications such as improved reliability, reduced leakage currents and for tuning voltage coefficients of the capacitor.

Abstract: A system and method for implementing multi-level resolution conversion (MLRC) of a set of image pixels efficiently using linear interpolation. The system automatically generates equations for determining the values of output pixels in a real-time manner as a function of the input pixels and a desired resolution conversion. As the input pixel values are received, the MLRC system generates the pixel values in real-time at a rate required for the output resolution without requiring a large number of intermediate complex calculations to be stored in memory. The pixel values utilized in the equations are normalized and scaled to values within a predetermined normalization range in order to minimize the complexity of the calculations performed by the MLRC system.

Abstract: A digital FIR filter is provided that inputs a series of data samples x[0] . . . x[n] and generates a partial sum output PS[i], where i≦n. The partial sum output is a weighted version of the a difference between a partial sum of the previous i−1 data samples, PS[i−1], and the current data sample x[n] added to the current data sample x[n]. The filter includes a plurality of weighting stages. Each weighting stage includes a first adder for subtracting the current data sample x[n] from the previous partial sum PS[i−1], a multiplier that multiplies the difference by a weighting coefficient, and a second adder that sums the weighted difference with the current data sample. The filter also includes a plurality of delay elements, each of which inputs a partial sum and imposes a unit delay on the partial sum before supplying it to a weighting stage.

Abstract: The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Abstract: A full-featured data access arrangement (DAA) for connecting a modem to a public switched telephone network (PSTN) includes a bridge current loop circuit, a line in use detection circuit, an off hook relay, a loop current sense circuit, and an extension/remote event detector circuit. The off hook relay is connected in series with the current loop circuit to enable the DAA to detect external off hook and on hook events when the modem is in an on hook state. The DAA is configured to detect the off hook and subsequent on hook status of an extension telephone at a location even though the modem and a handset sharing a line connector with the modem are both in an on hook state. The DAA is also capable of detecting an off hook state of an extension telephone even though the modem is in an off hook state. In addition, the DAA can detect when a remote telephone device that initiates an incoming call is placed on hook.

Abstract: Methods to recover spread spectrum radio signals are provided. A representative method includes recovering clock information from a plurality of signals from emitted from at least one basestation, aligning the plurality of signals using the recovered clock information, combining at least two of the aligned signals, and recovering information from the combined signal. Systems and other methods are also provided.

Abstract: A system is disclosed for improving the operation of a circuit having one or more semiconductor devices as temperature varies over the circuit's typical range of operating temperatures. In an environment of a current mirror, the invention can be used to reduce variation in the reference current as temperature changes. This is particularly desirable at low operating voltages. In one embodiment, the invention is configured as a current compensation module connected to a current mirror regulator node. At normal temperature, the current mirror reference current and the compensation module are configured to provide the desired amount of reference current to the current mirror. At temperatures above normal, the current compensation module automatically conducts more current than at normal temperature. At temperatures below normal, the current compensation module conducts less current than at normal temperature.

Abstract: An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.

Abstract: A multiple channel signal processing circuit receives an input associated with a first channel and an input associated with a second channel. The respective inputs are sampled and processed by the circuit, which generates a sampled output signal for the first channel and a sampled output signal for the second channel. The circuit employs a shared active circuit component, such as an operational amplifier, to alternately process samples associated with the first and second channels. A network of switches are controlled by a multiphase clock signal such that the active circuit component processes samples associated with only one channel at a time; as the input for a first channel is being sampled, a previous sample for the second channel is processed. An alternate circuit embodiment may be utilized to reduce the amount of crosstalk between the channels.

Abstract: A modem utilizing a DAA having line side circuitry including a telephone network interface and system side circuitry including a host system interface. The line side circuitry and the system side circuitry are separated by a high voltage isolation barrier. In accordance with the invention, the high voltage isolation barrier and other DAA circuitry are configured such that data and control information may be communicated between the system side circuitry and the line side circuitry using a serialized digital communication protocol. In one embodiment of the invention, the line side circuitry of the modem includes detection and measurement circuitry that is programmable to measure or establish electrical characteristics (e.g., tip/ring voltage and loop current) of the telephone line interface connection. Command information for the programmable circuitry is multiplexed with data communicated across the high voltage isolation barrier.