Abstract: A speech-coding system provides improved speech coding by injecting high-frequency noise into an output of a pulse codebook. A filtered noise is generated by passing a high frequency noise signal through a high pass filter. The filtered high frequency noise is injected into the pulse output of the codebook through convolution. The combined noise signal and pulse output generates a perceptually improved encoded speech signal.

Abstract: GPS satellites broadcast GPS signals with low power transmitters less than 50 watts. Although the GPS broadcast signals are encoded using spread spectrum technology which decreases the effect noise has on the reception of the signal, jamming signals can adversely affect GPS receiver performance. Jamming signals can cause position and velocity indication within the system to be erroneous. These errors can build up within the system and the errors may take a significant time to dissipate even after the jamming signal has gone. These errors can manifest themselves as errors in velocity and errors in position on the order of tens of miles. Methods of detection of the presence of the jamming signal including observing the output of a correlator chain in which the PN code being correlated is delayed in each link in the chain are presented in this disclosure. The present disclosure also proposes countermeasures for dealing with the jamming signal.

Abstract: A multi-rate speech codec supports a plurality of encoding bit rate modes by adaptively selecting encoding bit rate modes to match communication channel restrictions. In higher bit rate encoding modes, an accurate representation of speech through CELP (code excited linear prediction) and other associated modeling parameters are generated for higher quality decoding and reproduction. To support lower bit rate encoding modes, a variety of techniques,are applied many of which involve the classification of the input signal. The speech encoder continuously warps a weighted speech signal in long term preprocessing. The continuous warping is applied to a linear pitch lag contour that enables fast searching through linear time weighting. Optimal searching is performed within a limited range that is defined at least in part on sharpness and speech classification. The speech encoder generates the linear pitch lag contour from previous and current pitch lag values.

Abstract: An improved excitation enhancement system is provided for speech coding systems. As speech data applications continue to operate in areas having intrinsic bandwidth limitations, the perceptual quality of reproduced speech data in typical speech coding systems suffers. The invention employs short term enhancement to improve perceptual quality in reproduced speech. The short term enhancement is may be performed on the fixed codebook in eXtended code excited linear prediction (eX CELP) or may be performed as post-processing in the decoder.

Abstract: A method and apparatus for distributing the data error correction and compression processing load between a modem (DCE) and a host data terminal equipment (DTE) enables modem implementation with minimal cost, power dissipation, and size. The DTE has a CPU and an associated memory. The memory contains a data transmission program for execution by the CPU to produce output data for transmitting, and at least a data compression algorithm and a data error checking algorithm for execution by the CPU under control of the data transmission program to asynchronously deliver data according to the data transmission program to a modem for synchronous transmission. The modem included in the DCE asynchronously received the data from the DTE and synchronously transmits it as output data. Due to the distribution of the data processing algorithms into the memory of the DTE, the DCE can be operated simultaneously in communication and control modes.

Abstract: Equalizer training is validated by techniques to detect false training. The validation techniques involve checking the unique time domain energy shaping of a plurality of taps of a trained equalizer of a modem for good training. The energy measure for each equalizer tap of the plurality of taps is approximated by summing the magnitude of a real component and a magnitude of an imaginary component of an equalizer coefficient corresponding to the equalizer tap. A tap with a highest approximate energy (i.e., the main tap) is then determined. Next, the main tap energy is compared to a main tap threshold and a predetermined guarding threshold. The plurality of taps are arranged in a time index ordered sequence. In determining the main tap threshold, a first energy sum of a beginning set of taps in the sequence is compared with a second energy sum of a last set of taps in the sequence. The lesser tap energy sum between the first energy sum and the second energy sum is the main tap threshold.

Abstract: An electrostatic discharge protection circuit for protecting the output of a CMOS circuit includes the use of a saturation attenuation resistor in series with the output. The saturation attenuation resistor exhibits a low resistance value under low current conditions and a high resistance value under high current conditions. The saturation resistor in series with the output of a CMOS circuit thus has little effect on the current drive capability of that circuit during its normal operation. Upon the application of a high current ESD transient to the output, however, the saturation resistor assumes a high resistance value that acts to attenuate the voltage of the transient and protect the delicate gate dielectric of transistors at the output of the circuit.

Abstract: A digital subscriber line communication system does not require the use of a plain old telephone service (POTS) splitter in the resident's home. Digital signal processing techniques are utilized to adapt to varying subscriber line conditions due to POTS telephone equipment. The digital signal processing techniques eliminate the need for a splitter by reducing susceptibility to distortion due to varying subscriber line characteristics. The digital subscriber line modem characterizes the subscriber line under a variety of conditions when the modem is in a non-idle mode. The digital subscriber line modem includes a control circuit which performs rapid retrain operation utilizing line characterization information.

Abstract: A variable gain amplifier that has a high linearity gain stage coupled with a low noise gain stage, and a steering circuit that steers the input signal between these two stages depending on the gain requirement. The preferred embodiment employs steering of the input signal and extensive linearization (in dB) of the control signal to provide stable and linear gain control and high dynamic range.

Abstract: A method and apparatus which reduces the computational complexity of a receiver subject to power swings in excess of the power swings inherent in wireless communication from normal fading. To accomplish this, attenuation or some other form of signal modification occurs prior to the digital circuitry to reduce the required resolution of the analog to digital converter and other receiver components. A power signal estimator in conjunction with an attenuation control module may control the level of attenuation.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance.

Abstract: A semiconductor die with an imager sensor on an integrated circuit (IC) is mated directly to a substrate, such as a printed circuit board or any traditional chip carrier. A retaining well is built by adding an elevated structure about the mated IC chip with an inexpensive epoxy compound, forming a recess in which the IC is disposed. Thereafter, a coating layer of a viscous epoxy is added to the well and allowed to cure. The coating is clear, allowing light to pass to the IC chip. The epoxy along with the substrate encapsulates the IC chip, providing an easy and inexpensive chip package. The substrate may comprise a laminate substrate that is preprinted with easily reconfigurable leads and multi-layer routing arranged to minimize noise and cross-talk. The coating, or an additional coating placed on top of or underneath the clear coating, may also perform filtering of one or more portions of the light spectrum.

Abstract: The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

Abstract: An apparatus and method for converting pixel data from a computer video format to a television-compatible composite video waveform. A color space converter converts RGB or YCrCb pixel data into YUV pixel data. The YUV pixel data is supplied to an encoder which encodes the data into a composite video waveform. A clock generator generates an encoder clock frequency based on the horizontal resolution of the incoming computer pixel data. The encoder clock frequency is sufficient to allow encoding of all incoming pixels in the active video portion of the waveform without physically scaling or altering the pixel data. Sync and burst processors in the encoder encode sync pulses and burst waveforms at proper timing intervals despite the variable encoder clock frequency by accessing sync pulse and burst waveform values and timing parameters appropriate to ranges of clock frequencies that are stored in a ROM.

Abstract: An electronic bridge for providing a first electronic device attached to a high-data throughput bus and a second electronic device attached to a peripheral bus. The bridge further has an output bus circuit for generating output bus signals onto the peripheral bus, the output bus comprising a peripheral data bus a peripheral address bus. The bridge also has an output size signal circuit for generating output size signals for indicating the number of bits being used for a data transfer over the peripheral data bus, and an output control signal circuit for generating a output control signals onto the peripheral bus.

Abstract: A communication system for transferring (Peripheral Component Interconnect) PCI and non-PCI data over a non-PCI bus is disclosed. The system bus is a non-PCI bus having an address bus and a data bus for communicating addresses and data. A PCI-compatible peripheral is coupled to the non-PCI bus for transmitting and receiving PCI-compatible data. A non-PCI device is also coupled to the non-PCI bus for transmitting and receiving non-PCI data. In addition, a slave device is also coupled to the non-PCI bus for receiving and transmitting non-PCI data and PCI data. A byte size control line capable of being driven by the PCI-compatible peripheral and the non-PCI device is coupled between the PCI-compatible peripheral, the non-PCI device, and the slave device for indicating whether data appearing on the data bus is from the PCI-compatible peripheral or the non-PCI device, and for indicating how many bytes on the data bus are actually valid, if the data appearing on the non-PCI bus is from the non-PCI device.

Abstract: A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

Abstract: One disclosed embodiment comprises a vertical scaler receiving a first number of video lines at a first frequency. The vertical scaler outputs a second number of video lines at the first frequency. A FIFO has as an input from the vertical scaler the second number of video lines at the first frequency. The FIFO outputs the second number of video lines at a second frequency. Another disclosed embodiment further comprises a modulator/timing generator having as an input from the FIFO the second number of video lines at the second frequency. The second number of video lines can be in a first video format. The first video format can be a high resolution video format. The modulator/timing generator converts the second number of video lines in the first video format into a second video format. The second video format can be a low resolution video format.

Abstract: A method for preparing a speech signal for encoding comprises determining whether the spectral content of an input speech signal is representative of a defined spectral characteristic (e.g., a defined characteristic slope). A frequency specific filter component of a weighting filter is controlled based on the determination of the spectral content of the speech signal or/and its location in the encoder. A core weighting filter component of the weighting filter may be maintained regardless of the spectral content of the speech signal.